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Andrzej Krasniewski
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2010 – 2019
- 2014
- [c35]Grzegorz Borowik, Andrzej Krasniewski
, Tadeusz Luba:
Rule Induction Based on Logic Synthesis Methods. ICSEng 2014: 813-816 - 2012
- [c34]Jakub Korczyc, Andrzej Krasniewski
Evaluation of susceptibility of FPGA-based circuits to fault injection attacks based on clock glitching. DDECS 2012: 171-174 - 2011
- [c33]Grzegorz Borowik, Andrzej Krasniewski
Trading-Off Error Detection Efficiency with Implementation Cost for Sequential Circuits Implemented with FPGAs. EUROCAST (2) 2011: 327-334 - [c32]Grzegorz Borowik, Andrzej Krasniewski
A Tool for Trading-Off On-Line Error Detection Efficiency with Implementation Cost for Sequential Logic Implemented in FPGAs. ICSEng 2011: 488-489
2000 – 2009
- 2008
- [j4]Andrzej Krasniewski:
Concurrent error detection for finite state machines implemented with embedded memory blocks of SRAM-based FPGAs. Microprocess. Microsystems 32(5-6): 303-312 (2008) - [c31]Andrzej Krasniewski:
Concurrent Error Detection for Combinational Logic Blocks Implemented with Embedded Memory Blocks of FPGAs. DDECS 2008: 74-79 - [c30]Andrzej Krasniewski:
Concurrent Error Detection for a Network of Combinational Logic Blocks Implemented with Memory Embedded in FPGAs. DSD 2008: 250-255 - 2007
- [c29]Andrzej Krasniewski:
Concurrent Error Detection for FSMs Designed for Implementation with Embedded Memory Blocks of FPGAs. DSD 2007: 579-586 - [e1]Patrick Girard, Andrzej Krasniewski, Elena Gramatová, Adam Pawlak, Tomasz Garbolino:
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007. IEEE Computer Society 2007, ISBN 1-4244-1161-0 [contents] - 2006
- [c28]Andrzej Krasniewski:
Low-Cost Concurrent Error Detection for FSMs Implemented Using Embedded Memory Blocks of FPGAs. DDECS 2006: 180-185 - 2005
- [c27]Andrzej Krasniewski
A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory. IOLTS 2005: 197-198 - 2004
- [c26]Andrzej Krasniewski:
Concurrent Error Detection in Sequential Circuits Implemented Using Embedded Memory of LUT-Based FPGAs. DFT 2004: 487-495 - [c25]Andrzej Krasniewski:
Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory. FPL 2004: 1067-1072 - [c24]Andrzej Krasniewski:
Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory Blocks. IOLTS 2004: 67-72 - 2003
- [j3]Andrzej Krasniewski
Evaluation of delay fault testability of LUTs for the enhancement of application-dependent testing of FPGAs. J. Syst. Archit. 49(4-6): 283-296 (2003) - [c23]Andrzej Krasniewski
Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices. FPL 2003: 828-838 - [c22]Andrzej Krasniewski:
Evaluation of the Quality of Testing Path Delay Faults under Restricted Input Assumption. IOLTS 2003: 168- - 2002
- [c21]Andrzej Krasniewski:
On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs. FPL 2002: 596-606 - [c20]Andrzej Krasniewski:
Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs. FPL 2002: 616-626 - 2001
- [c19]Andrzej Krasniewski:
Evaluation of Delay Fault Testability of LUT Functions for Improved Efficiency of FPGA Testing. DSD 2001: 310-317 - [c18]Andrzej Krasniewski
Testing FPGA Delay Faults in the System Environment is Very Different from "Ordinary" Delay Fault Testing. IOLTW 2001: 37- - 2000
- [c17]Andrzej Krasniewski
Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAs. FPL 2000: 675-684 - [c16]Andrzej Krasniewski
Self-Testing of FPGA Delay Faults in the System Environment. IOLTW 2000: 40-
1990 – 1999
- 1999
- [c15]Pawel Tomaszewicz
Self-Testing of S-Compatible Test Units in User-Programmed FPGAs. EUROMICRO 1999: 1254-1259 - [c14]Andrzej Krasniewski
Application-Dependent Testing of FPGA Delay Faults. EUROMICRO 1999: 1260-1267 - 1996
- [c13]Andrzej Krasniewski:
Design of Dependable Hardware: What BIST is most Efficient? EDCC 1996: 233-245 - 1994
- [c12]Andrzej Krasniewski, Leszek B. Wronski:
Coverage of Delay Faults: When 13% and 99% Mean the Same. EDCC 1994: 178-195 - [c11]Andrzej Krasniewski, Leszek B. Wronski:
Tests for path delay faults vs. tests for gate delay faults: how different they are. EURO-DAC 1994: 310-315 - 1992
- [j2]Slawomir Pilarski, Andrzej Krasniewski
Estimating testing effectiveness of the circular self-test path technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(10): 1301-1316 (1992) - [c10]Xiaodong Xie, Alexander Albicki, Andrzej Krasniewski:
Design of Robust-Path-Delay-Fault-Testable Combinational Circuits by Boolean Space Expansion. ICCD 1992: 482-485 - [c9]Andrzej Krasniewski, Slawomir Pilarski:
High Quality Testing of Embedded RAMs Using Circular Self-Test Path. ITC 1992: 652-661 - 1991
- [c8]Andrzej Krasniewski
Logic Synthesis for Efficient Pseudoexhaustive Testability. DAC 1991: 66-72 - [c7]Andrzej Krasniewski, Alexander Albicki:
Random Testability of Redundant Circuits. ICCD 1991: 424-427 - [c6]Andrzej Krasniewski:
Can Redundancy Enhance Testability? ITC 1991: 483-491 - 1990
- [c5]Andrzej Krasniewski
Design for verification testability. EURO-DAC 1990: 644-648
1980 – 1989
- 1989
- [j1]Andrzej Krasniewski
Circular self-test path: a low-cost BIST technique for VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(1): 46-55 (1989) - 1987
- [c4]Andrzej Krasniewski, Slawomir Pilarski:
Circular Self-Test Path: A Low-Cost BIST Technique. DAC 1987: 407-415 - 1985
- [c3]Andrzej Krasniewski, Alexander Albicki:
Simulation-free estimation of speed degradation in NMOS self-testing circuits for CAD applications. DAC 1985: 808-811 - [c2]Andrzej Krasniewski, Alexander Albicki:
Automatic Design of Exhaustively Self-Testing Chips with Bilbo Modules. ITC 1985: 362-371 - 1984
- [c1]Andrzej Krasniewski:
Fuzzy Automata as Adaptive Algorithms for Telephone Traffic Routing. ICC (1) 1984: 61-66
Coauthor Index
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