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Seon-Yong Cha
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2020 – today
- 2022
- [j2]Jihyo Kang
, Jaehyeok Yang
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation. IEEE J. Solid State Circuits 57(1): 212-223 (2022) - 2021
- [c1]Kyunghoon Kim, Joo-Hyung Chae
A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation. ISSCC 2021: 344-346
2010 – 2019
- 2012
- [j1]In-Young Chung, Seong Yeol Jeong, Sung Min Seo, Myungjin Lee, Taesu Jang, Seon-Yong Cha, Young June Park:
New Multiple-Times Programmable CMOS ROM Cell. IEICE Trans. Electron. 95-C(6): 1098-1103 (2012)
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last updated on 2024-04-24 23:11 CEST by the dblp team
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