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Massimo Pozzoni
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2010 – 2019
- 2019
- [j5]Emanuele Depaoli
, Hongyang Zhang, Marco Mazzini
A 64 Gb/s Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm FDSOI CMOS. IEEE J. Solid State Circuits 54(1): 6-17 (2019) - 2018
- [c8]Emanuele Depaoli, Enrico Monaco, Giovanni Steffan, Marco Mazzini, Hongyang Zhang, Walter Audoglio, Oscar Belotti, Augusto Andrea Rossi, Guido Albasini, Massimo Pozzoni, Simone Erba, Andrea Mazzanti:
A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR transceiver in 28nm FDSOI CMOS. ISSCC 2018: 112-114 - 2013
- [c7]Francesco Radice, Melchiorre Bruccoleri, Marcello Ganzerli, Giorgio Spelgatti, Davide Sanzogni, Massimo Pozzoni, Andrea Mazzanti:
A 6-bit 6-GS/s 95mW background calibrated flash ADC with integrating preamplifiers and half-rate comparators in 32nm LP CMOS. ESSCIRC 2013: 129-132 - 2011
- [j4]Federico Vecchi, Stefano Bozzola, Enrico Temporiti, Davide Guermandi, Massimo Pozzoni, Matteo Repossi
A Wideband Receiver for Multi-Gbit/s Communications in 65 nm CMOS. IEEE J. Solid State Circuits 46(3): 551-561 (2011) - 2010
- [j3]Enrico Monaco, Massimo Pozzoni, Francesco Svelto, Andrea Mazzanti:
Injection-Locked CMOS Frequency Doublers for μ -Wave and mm-Wave Applications. IEEE J. Solid State Circuits 45(8): 1565-1574 (2010) - [c6]Massimo Pozzoni, Simone Erba, Davide Sanzogni, Marcello Ganzerli, Paolo Viola, Daniele Baldi, Matteo Repossi
A 12Gb/s 39dB loss-recovery unclocked-DFE receiver with bi-dimensional equalization. ISSCC 2010: 164-165 - [c5]Federico Vecchi, Stefano Bozzola, Massimo Pozzoni, Davide Guermandi, Enrico Temporiti, Matteo Repossi
A wideband mm-Wave CMOS receiver for Gb/s communications employing interstage coupled resonators. ISSCC 2010: 220-221 - [c4]Andrea Mazzanti, Enrico Monaco, Massimo Pozzoni, Francesco Svelto:
A 13.1% tuning range 115GHz frequency generator based on an injection-locked frequency doubler in 65nm CMOS. ISSCC 2010: 422-423
2000 – 2009
- 2009
- [j2]Massimo Pozzoni, Simone Erba, Paolo Viola, Matteo Pisati, Emanuele Depaoli, Davide Sanzogni, Riccardo Brama, Daniele Baldi, Matteo Repossi
A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication. IEEE J. Solid State Circuits 44(4): 1306-1315 (2009) - [c3]Stefano Bozzola, Davide Guermandi, Federico Vecchi, Matteo Repossi
A sliding IF receiver for mm-wave WLANs in 65nm CMOS. CICC 2009: 669-672 - 2008
- [c2]Simone Erba, Massimo Pozzoni, Matteo Pisati, Riccardo Brama
A 10Gb/s receiver with linear backplane equalization and mixer-based self-aligned CDR. CICC 2008: 559-562 - 2005
- [j1]Francesco Centurelli
A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability. IEEE Trans. Very Large Scale Integr. Syst. 13(2): 191-200 (2005) - 2004
- [c1]Francesco Centurelli, Massimo Pozzoni, Giuseppe Scotti, Alessandro Trifiletti:
A high-speed low-voltage phase detector for clock recovery from NRZ data. ISCAS (4) 2004: 297-300
Coauthor Index
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