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Almudena Lindoso
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2020 – today
- 2024
- [j14]Luis Ángel García-Astudillo
, Almudena Lindoso
Error Mitigation Using Optimized Redundancy for Composite Algorithms in FPGAs. IEEE Trans. Aerosp. Electron. Syst. 60(2): 2143-2152 (2024) - [j13]German Leon
Comparative analysis of soft-error sensitivity in LU decomposition algorithms on diverse GPUs. J. Supercomput. 80(9): 12844-12862 (2024) - 2023
- [j12]Luis Entrena
Formal Verification of Fault-Tolerant Hardware Designs. IEEE Access 11: 116127-116140 (2023) - [j11]Pablo M. Aviles
Supervised Triple Macrosynchronized Lockstep (STMLS) Architecture for Multicore Processors. IEEE Access 11: 128706-128723 (2023) - [j10]Diego Lloria, Pablo M. Aviles
Hybrid CPU-GPU implementation of the transformed spatial domain channel estimation algorithm for mmWave MIMO systems. J. Supercomput. 79(9): 9371-9382 (2023) - 2022
- [j9]Luis Ángel García-Astudillo
Reduced Resolution Redundancy: A Novel Approximate Error Mitigation Technique. IEEE Access 10: 20643-20651 (2022) - [j8]Pablo M. Aviles
Performance analysis of a millimeter wave MIMO channel estimation method in an embedded multi-core processor. J. Supercomput. 78(12): 14756-14767 (2022) - [c10]Pablo M. Aviles
Acceleration of the TSDCE MIMO Channel Estimation Algorithm on a Multi-core Platform. EATIS 2022: 15:1-15:4 - 2021
- [j7]Jose A. Belloch
Evaluating the computational performance of the Xilinx Ultrascale+ EG Heterogeneous MPSoC. J. Supercomput. 77(2): 2124-2137 (2021) - 2020
- [c9]Luis Ángel García-Astudillo
Evaluation of a Reduced Precision Redundancy FFT Design. DCIS 2020: 1-6
2010 – 2019
- 2018
- [j6]Manuel Peña-Fernandez, Almudena Lindoso
PTM-based hybrid error-detection architecture for ARM microprocessors. Microelectron. Reliab. 88-90: 925-930 (2018) - 2016
- [j5]Boyang Du
Online Test of Control Flow Errors: A New Debug Interface-Based Approach. IEEE Trans. Computers 65(6): 1846-1855 (2016) - [j4]Antonio Martínez-Álvarez
A Hardware-Software Approach for On-Line Soft Error Mitigation in Interrupt-Driven Applications. IEEE Trans. Dependable Secur. Comput. 13(4): 502-508 (2016) - 2014
- [c8]Boyang Du
A new solution to on-line detection of Control Flow Errors. IOLTS 2014: 105-110 - 2013
- [c7]Boyang Du
Exploiting the debug interface to support on-line test of control flow errors. IOLTS 2013: 98-103 - 2012
- [j3]Marta Portela-García
Evaluating the Effectiveness of a Software-Based Technique Under SEEs Using FPGA-Based Fault Injection Approach. J. Electron. Test. 28(6): 777-789 (2012) - [j2]Luis Entrena
Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection. IEEE Trans. Computers 61(3): 313-322 (2012) - 2011
- [c6]Marta Portela-García
Using an FPGA-based fault injection technique to evaluate software robustness under SEEs: A case study. LATW 2011: 1-6
2000 – 2009
- 2008
- [c5]Almudena Lindoso
Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC. FPL 2008: 539-542 - 2007
- [j1]Almudena Lindoso
High performance FPGA-based image correlation. J. Real Time Image Process. 2(4): 223-233 (2007) - [c4]Almudena Lindoso, Luis Entrena, Judith Liu-Jimenez:
Wavelet-Based Fingerprint Region Selection. CAIP 2007: 391-398 - [c3]Almudena Lindoso, Luis Entrena, Judith Liu-Jimenez, Enrique San Millán:
Correlation-Based Fingerprint Matching with Orientation Field Alignment. ICB 2007: 713-721 - 2006
- [c2]Judith Liu-Jimenez, Raul Sánchez-Reillo
FPGA implementation for an iris biometric processor. FPT 2006: 265-268 - 2005
- [c1]Almudena Lindoso, Luis Entrena, Celia López-Ongil, Judith Liu-Jimenez:
Correlation-Based Fingerprint Matching Using FPGAs. FPT 2005: 87-94
Coauthor Index
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