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Laurence E. Turner
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2000 – 2009
- 2006
- [c20]Dan Cyca, Laurence E. Turner:
Bit-Serial Digital Filter Implementation using a Custom C Compiler. APCCAS 2006: 534-537 - [c19]Dan Cyca, Laurence E. Turner:
A C compiler for implementing FPGA based bit-serial DSP systems. FPT 2006: 305-308 - 2004
- [c18]Sean E. Krakiwsky, Laurence E. Turner, Michal M. Okoniewski:
Graphics processor unit (GPU) acceleration of finite-difference time-domain (FDTD) algorithm. ISCAS (5) 2004: 265-268 - [c17]S. A. Rahim, Laurence E. Turner:
A Field Programmable Bit-Serial Digital Signal Processor. IWSOC 2004: 295-298 - 2003
- [j2]Trevor W. Fox, Laurence E. Turner:
Rapid Prototyping of Field Programmable Gate Array-Based Discrete Cosine Transform Approximations. EURASIP J. Adv. Signal Process. 2003(6): 543-554 (2003) - [j1]Alex Carreira, Trevor W. Fox, Laurence E. Turner:
A Methodology for Rapid Prototyping Peak-Constrained Least-Squares Bit-Serial Finite Impulse Response Filters in FPGAs. EURASIP J. Adv. Signal Process. 2003(6): 555-564 (2003) - [c16]Trevor W. Fox, Alex Carreira, Laurence E. Turner:
The Design of Low-Power Fixed-Point FIR Differentiator IP Blocks. IWSOC 2003: 53-58 - 2002
- [c15]Ryan N. Schneider, Laurence E. Turner, Michal M. Okoniewski:
Application of FPGA technology to accelerate the finite-difference time-domain (FDTD) method. FPGA 2002: 97-105 - [c14]Alex Carreira, Trevor W. Fox, Laurence E. Turner:
A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBitsTM. FPL 2002: 222-231 - [c13]Trevor W. Fox, Laurence E. Turner:
Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA. FPL 2002: 492-502 - [c12]Alex Carreira, Trevor W. Fox, Laurence E. Turner:
A method of implementing bit-serial LDI ladder filters in FPGAs using JBits. FPT 2002: 433-436 - [c11]Trevor W. Fox, Laurence E. Turner:
Low coefficient complexity approximations of the one dimensional discrete cosine transform. ISCAS (1) 2002: 285-288 - [c10]S. G. Gibb, Laurence E. Turner:
The Automatic Generation of Application Specific Processors. IWLS 2002: 161-165 - 2001
- [c9]Trevor W. Fox, Laurence E. Turner:
The design of peak constrained least squares FIR filters with low complexity finite precision coefficients. ISCAS (2) 2001: 605-608
1990 – 1999
- 1997
- [c8]T. Mathews, S. G. Gibb, Laurence E. Turner, Peter J. W. Graumann, Michel Fattouche:
An FPGA implementation of a matched filter detector for spread spectrum communications systems. FPL 1997: 364-373 - 1995
- [c7]Laurence E. Turner, Peter J. W. Graumann:
Rapid Hardware Prototyping of Digital Signal Processing Systems Using FPGAs. FPL 1995: 129-138 - [c6]Gopal Panneerselvam, Peter J. W. Graumann, Laurence E. Turner:
Implementation of Fast Fourier Transforms and Discrete Cosine Transforms in FPGAs. FPL 1995: 272-281 - [c5]Laurence E. Turner, Peter J. W. Graumann, S. G. Gibb:
BIT-Serial FIR Filters with CSD Coefficients for FPGAs. FPL 1995: 311-320 - 1994
- [c4]Bruce A. Johnston, Peter J. W. Graumann, Laurence E. Turner:
DSP System Synthesis Including Variable Data Path Width. ISCAS 1994: 53-56 - 1993
- [c3]Stephen Worthington, Laurence E. Turner:
A method of evaluating the effects of signal quantization at arbitrary locations in recursive digital filters. ISCAS 1993: 615-618 - 1991
- [c2]R. Nagalla, Laurence E. Turner:
Pipelined BIT-Serial SYNthesis of Digital Filerting Algorithms. VLSI 1991: 39-48
1980 – 1989
- 1984
- [c1]Laurence E. Turner, Peter B. Denyer, David Renshaw:
A bit serial LDI recursive digital filter. ICASSP 1984: 238-241
Coauthor Index
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