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Mu-Tien Chang
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2010 – 2019
- 2018
- [c10]Mu-Tien Chang, I. Stephen Choi, Dimin Niu, Hongzhong Zheng:
Performance Impact of Emerging Memory Technologies on Big Data Applications: A Latency-Programmable System Emulation Approach. ACM Great Lakes Symposium on VLSI 2018: 439-442 - 2017
- [c9]Krishna T. Malladi, Mu-Tien Chang, Dimin Niu, Hongzhong Zheng:
FlashStorageSim: Performance Modeling for SSD Architectures. NAS 2017: 1-2 - [c8]Tyler Stocksdale, Mu-Tien Chang, Hongzhong Zheng, Frank Mueller:
Architecting HBM as a high bandwidth, high capacity, self-managed last-level cache. PDSW-DISCS@SC 2017: 31-36 - 2016
- [j1]Ishwar Bhati, Mu-Tien Chang, Zeshan Chishti, Shih-Lien Lu, Bruce L. Jacob:
DRAM Refresh Mechanisms, Penalties, and Trade-Offs. IEEE Trans. Computers 65(1): 108-121 (2016) - 2015
- [c7]Krishna T. Malladi, Mu-Tien Chang, John Ping, Hongzhong Zheng:
FAME: A Fast and Accurate Memory Emulator for New Memory System Architecture Exploration. MASCOTS 2015: 43-46 - 2013
- [c6]Mu-Tien Chang, Paul Rosenfeld, Shih-Lien Lu, Bruce L. Jacob:
Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM. HPCA 2013: 143-154 - 2012
- [c5]Mu-Tien Chang, Joe Gross, Bruce L. Jacob:
Energy-Efficient Cached DIMM Architecture. MASCOTS 2012: 501-503 - 2011
- [c4]Mu-Tien Chang, Bruce L. Jacob:
An analytical model to estimate PCM failure probability due to process variations. SoCC 2011: 174-177
2000 – 2009
- 2008
- [c3]Mu-Tien Chang, Wei Hwang:
A fully-differential subthreshold SRAM cell with auto-compensation. APCCAS 2008: 1771-1774 - [c2]Mu-Tien Chang, Po-Tsang Huang, Wei Hwang:
A robust ultra-low power asynchronous FIFO memory with self-adaptive power control. SoCC 2008: 175-178 - 2007
- [c1]Mu-Tien Chang, Po-Tsang Huang, Wei Hwang:
A 65nm low power 2T1D embedded DRAM with leakage current reduction. SoCC 2007: 207-210
Coauthor Index
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