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Yasuki Tanabe
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2020 – today
- 2020
- [j2]Yutaka Yamada
, Masato Uchiyama, Masashi Jobashi, Tomohiro Koizumi, Takanori Tamai, Nobuhiro Sato, Jun Tanabe, Katsuyuki Kimura, Yoshinari Ojima
A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications. IEEE J. Solid State Circuits 55(1): 120-132 (2020)
2010 – 2019
- 2019
- [c10]Yutaka Yamada, Toru Sano, Yasuki Tanabe, Yutaro Ishigaki
A 20.5TOPS and 217.3GOPS/mm2 Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications. ISSCC 2019: 132-134 - 2018
- [c9]Jinhang Choi
A Power-Efficient Hybrid Architecture Design for Image Recognition Using CNNs. ISVLSI 2018: 22-27 - 2015
- [c8]Nau Ozaki, Masato Uchiyama, Yasuki Tanabe, Shuichi Miyazaki, Takaaki Sawada, Takanori Tamai, Moriyasu Banno:
Implementation and evaluation of image recognition algorithm for an intelligent vehicle using heterogeneous multi-core SoC. ASP-DAC 2015: 410-415 - [c7]Siddharth Advani, Brigid Smith, Yasuki Tanabe, Kevin M. Irick, Matthew Cotter, Jack Sampson, Vijaykrishnan Narayanan:
Visual co-occurrence network: using context for large-scale object recognition in retail. ESTIMedia 2015: 1-10 - [c6]Siddharth Advani, Yasuki Tanabe, Kevin M. Irick, Jack Sampson, Vijaykrishnan Narayanan:
A scalable architecture for multi-class visual object detection. FPL 2015: 1-8 - 2012
- [c5]Masato Uchiyama, Hideho Arakida, Yasuki Tanabe, Tsukasa Ike, Takanori Tamai, Moriyasu Banno:
Visconti2 - a heterogeneous multi-core SoC for image-recognition applications. Hot Chips Symposium 2012: 1-22 - [c4]Yasuki Tanabe, Masato Sumiyoshi, Manabu Nishiyama, Itaru Yamazaki, Shinsuke Fujii, Katsuyuki Kimura, Takuma Aoyama, Moriyasu Banno, Hiroo Hayashi, Takashi Miyamori:
A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications. ISSCC 2012: 222-223
2000 – 2009
- 2005
- [j1]Takashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Yasuki Tanabe, Toshihiro Hanawa
The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism). Parallel Comput. 31(3-4): 352-370 (2005) - [c3]Toshihiro Hanawa, Toshiya Minai, Yasuki Tanabe, Hideharu Amano:
Implementation of ISIS-SimpleScalar. PDPTA 2005: 117-123 - 2004
- [c2]Masato Sumiyoshi, Takashi Midorikawa, Yasuki Tanabe, Hideharu Amano:
Design and Evaluation of a Switch Architecture for Multistage Interconnection Network with Temporary Directory. PDCS 2004: 296-301 - 2003
- [c1]Yasuki Tanabe, Takashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Toshihiro Hanawa, Hideharu Amano:
Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism. PDPTA 2003: 1148-1154
Coauthor Index
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