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Yutaro Ishigaki
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2020 – today
- 2020
- [j2]Yutaka Yamada
, Masato Uchiyama, Masashi Jobashi, Tomohiro Koizumi, Takanori Tamai, Nobuhiro Sato, Jun Tanabe, Katsuyuki Kimura, Yoshinari Ojima
A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications. IEEE J. Solid State Circuits 55(1): 120-132 (2020)
2010 – 2019
- 2019
- [c3]Yutaka Yamada, Toru Sano, Yasuki Tanabe, Yutaro Ishigaki
A 20.5TOPS and 217.3GOPS/mm2 Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications. ISSCC 2019: 132-134 - 2015
- [c2]Yutaro Ishigaki
An FPGA-Based Accelerator for the 2D Implicit FDM and Its Application to Heat Conduction Simulations (Abstract Only). FPGA 2015: 266 - [c1]Yutaro Ishigaki
An FPGA implementation of 3D numerical simulations on a 2D SIMD array processor. ISCAS 2015: 938-941 - 2014
- [j1]Ryota Takasu, Yoichi Tomioka
An FPGA Implementation of the Two-Dimensional FDTD Method and Its Performance Comparison with GPGPU. IEICE Trans. Electron. 97-C(7): 697-706 (2014)
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last updated on 2024-08-05 21:14 CEST by the dblp team
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