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Journal of Low Power Electronics, Volume 4
Volume 4, Number 1, April 2008
- Peng Rong, Massoud Pedram:
Energy-Aware Task Scheduling and Dynamic Voltage Scaling in a Real-Time System. 1-10 - Mark Hempstead, Michael J. Lyons, David M. Brooks, Gu-Yeon Wei:
Survey of Hardware Systems for Wireless Sensor Networks. 11-20 - Antoine Courtay, Olivier Sentieys
, Johann Laurent, Nathalie Julien:
High-Level Interconnect Delay and Power Estimation. 21-33 - Kostas Siozios
Designing a General-Purpose Interconnection Architecture for Field Programmable Gate Arrays. 34-47 - Sachin Idgunji, David Flynn:
Design and Analysis of a Low Power Multi-Threshold CMOS Based ARM926 System. 48-59 - Hassen Aziza, Emmanuel Bergeret
A Novel Low Power Oriented Design Methodology for Analog Blocks. 60-67 - Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
Multi-Attribute Optimization with Application to Leakage-Delay Trade-Offs Using Utility Theory. 68-80 - Srivaths Ravi, Rubin A. Parekhji, Jayashree Saxena:
Low Power Test for Nanometer System-on-Chips (SoCs). 81-100 - V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti:
A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction. 101-110
Volume 4, Number 2, August 2008
- Christian Piguet, Jean-Luc Nagel, Vincent Peiris, Steve Gyger, Daniel Séverac, Marc-Nicolas Morgan, Jean-Marc Masgonty:
Low-Power Heterogeneous Systems-on-Chips. 111-126 - C. P. Ravikumar, Mokhtar Hirech, Xiaoqing Wen:
Test Strategies for Low-Power Devices. 127-138 - Sheldon X.-D. Tan, Pu Liu, Lin Jiang, Wei Wu, Murli Tirumala:
A Fast Architecture-Level Thermal Analysis Method for Runtime Thermal Regulation. 139-148 - Hanene Ben Fradj, Cécile Belleudy, Michel Auguin, Alain Pegatoquet:
Low Power Main Memory Configuration and Tasks Allocation. 149-157 - Anup Dandapat
Design of a Low Leakage, Low Power and High Performance Search and Read Memory Using CAM and SRAM. 158-168 - Giuseppe Visalli
Fuzzy Control of Coding Schemes for Reducing Energy Dissipation in Off-Chip Buses. 169-177 - V. S. Kanchana Bhaaskaran
Differential Cascode Adiabatic Logic Structure for Low Power. 178-190 - Tai-Hsuan Wu, Lin Xie, Azadeh Davoodi:
A Parallel and Randomized Algorithm for Large-Scale Discrete Dual-Vt Assignment and Continuous Gate Sizing. 191-201 - T. Parveen, M. T. Ahmed:
Simple Single Time Constant Circuits Using Low Voltage Operational Floating Conveyor. 202-207 - D. Meganathan
A 52.6 mW 10-bit, 100 MS/s Pipelined CMOS Analog-To-Digital Converter. 208-227 - Neila Rekik, Sinda Shabou, Ahmed Ben Hamida, Mounir Samet:
Programmable Current Source Design Dedicated to an Advanced Cochlear Implant Micro-Stimulator. 228-239 - R. Srinivasan, Navakanta Bhat:
Optimisation of Gate-Drain/Source Overlap in 90 nm NMOSFETs for Low Noise Amplifier Performance. 240-246
Volume 4, Number 3, December 2008
- Felipe Machado
A Binary Decision Diagram Structure for Probabilistic Switching Activity Estimation. 247-262 - B. P. Harish, Navakanta Bhat, Mahesh B. Patil:
Hybrid-CV Modeling for Estimating the Variability in Dynamic Power. 263-274 - Kostas Siozios
A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs. 275-289 - Enric Musoll:
Power Gating Clustered Many-Core Architectures. 290-300 - Janakiraman Viraraghavan
Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks. 301-319 - Omer Can Akgun
Energy Efficiency Comparison of Asynchronous and Synchronous Circuits Operating in the Sub-Threshold Regime. 320-336 - Andrew Bailey, Ahmad Al Zahrani, Guoyuan Fu, Jia Di, Scott C. Smith:
Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power. 337-348 - Michael Paynter, Taskin Koçak:
Design and Implementation of Low-Power Bloom Filters for Deep Packet Inspection. 349-359 - Jeremy Lee, Mohammad Tehranipoor:
Layout-Aware Transition-Delay Fault Pattern Generation with Evenly Distributed Switching Activity. 360-371 - Alex Bystrov
Selected Peer-Reviewed Articles from the LPonTR 2008 Workshop. 372-373 - Andrea Calimera
Thermal-Aware Design Techniques for Nanometer CMOS Circuits. 374-384 - Judit Freijedo, Jorge Semião
Delay Modeling for Power Noise and Temperature-Aware Design and Test of Digital Systems. 385-391 - Aswin Sreedhar, Sandip Kundu:
Lithography Simulation Basics and a Study on Impact of Lithographic Process Window on Gate and Path Delays. 392-401 - Ivano Midulla, Chouki Aktouf:
Test Power Analysis at Register Transfer Level. 402-409 - Jorge Semião
Time Management for Low-Power Design of Digital Systems. 410-419 - René Kothe, Heinrich Theodor Vierhaus:
A Scan Controller Concept for Low Power Scan Tests. 420-428 - Irith Pomeranz, Sudhakar M. Reddy:
Functional Broadside Tests with Minimum and Maximum Switching Activity. 429-437
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