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Mahmut E. Sinangil
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2020 – today
- 2024
- [c15]Sudhir S. Kudva, Mahmut Ersin Sinangil, Stephen G. Tell, Nikola Nedovic, Sanquan Song, Brian Zimmer, C. Thomas Gray:
16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking. ISSCC 2024: 302-304 - 2022
- [c14]Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Mei-Chen Chuang, Rawan Naous, Chao-Kai Chuang, Takeshi Hashizume, Dar Sun, Chia-Fu Lee, Kerem Akarvardar, Saman Adham, Tan-Li Chou, Mahmut Ersin Sinangil, Yih Wang
, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang:
A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations. ISSCC 2022: 1-3 - 2021
- [j13]Mahmut E. Sinangil
A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS. IEEE J. Solid State Circuits 56(1): 188-198 (2021) - [c13]Yu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, Yi-Chun Shih, Chia-Fu Lee, Rawan Naous, Yu-Lin Chen, Chieh-Pu Lo
An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications. ISSCC 2021: 252-254 - 2020
- [c12]Qing Dong, Mahmut E. Sinangil, Burak Erbagci, Dar Sun, Win-San Khwa, Hung-Jen Liao, Yih Wang
15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications. ISSCC 2020: 242-244
2010 – 2019
- 2019
- [j12]Qing Dong
A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination. IEEE J. Solid State Circuits 54(1): 231-239 (2019) - [j11]Mahmut E. Sinangil
A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell. IEEE J. Solid State Circuits 54(4): 1152-1160 (2019) - 2018
- [c11]Mahmut E. Sinangil, Yen-Ting Lin, Hung-Jen Liao, Jonathan Chang:
A 290MV Ultra-Low Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell in 7NM FinFET Technology. VLSI Circuits 2018: 13-14 - 2017
- [j10]Chuhong Duan
Energy-Efficient Reconfigurable SRAM: Reducing Read Power Through Data Statistics. IEEE J. Solid State Circuits 52(10): 2703-2711 (2017) - 2016
- [j9]Mahmut E. Sinangil, John W. Poulton, Matthew R. Fojtik, Thomas H. Greer, Stephen G. Tell, Andreas J. Gotterba, Jesse Wang, Jason Golbus, Brian Zimmer, William J. Dally, C. Thomas Gray:
A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation. IEEE J. Solid State Circuits 51(2): 557-567 (2016) - [c10]Chuhong Duan, Andreas J. Gotterba, Mahmut E. Sinangil, Anantha P. Chandrakasan:
Reconfigurable, conditional pre-charge SRAM: Lowering read power by leveraging data statistics. A-SSCC 2016: 177-180 - 2014
- [j8]Mahmut E. Sinangil, Anantha P. Chandrakasan:
Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9× Lower Energy/Access. IEEE J. Solid State Circuits 49(1): 107-117 (2014) - [c9]Arijit Banerjee
A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs. ISQED 2014: 1-8 - [c8]Yildiz Sinangil, Sabrina M. Neuman, Mahmut E. Sinangil, Nathan Ickes, George Bezerra, Eric Lau, Jason E. Miller, Henry Hoffmann, Srinivas Devadas, Anantha P. Chandrakasan:
A self-aware processor SoC using energy monitors integrated into power converters for self-adaptation. VLSIC 2014: 1-2 - 2013
- [j7]Mahmut E. Sinangil, Vivienne Sze, Minhua Zhou, Anantha P. Chandrakasan:
Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard. IEEE J. Sel. Top. Signal Process. 7(6): 1017-1028 (2013) - [c7]Mahmut E. Sinangil, Anantha P. Chandrakasan:
An SRAM using output prediction to reduce BL-switching activity and statistically-gated SA for up to 1.9× reduction in energy/access. ISSCC 2013: 318-319 - 2012
- [b1]Mahmut E. Sinangil:
Low-power and application-specific SRAM design for energy-efficient motion estimation. Massachusetts Institute of Technology, Cambridge, MA, USA, 2012 - [j6]Nathan Ickes, Gordon Gammie, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko:
A 28 nm 0.6 V Low Power DSP for Mobile Applications. IEEE J. Solid State Circuits 47(1): 35-46 (2012) - [j5]Mahmut E. Sinangil, Marcus Yip, Masood Qazi, Rahul Rithe, Joyce Kwong, Anantha P. Chandrakasan:
Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems. IEEE Trans. Circuits Syst. II Express Briefs 59-II(9): 533-537 (2012) - [c6]Henry Hoffmann, Jim Holt, George Kurian, Eric Lau, Martina Maggio
Self-aware computing in the Angstrom processor. DAC 2012: 259-264 - [c5]Mahmut E. Sinangil, Anantha P. Chandrakasan, Vivienne Sze, Minhua Zhou:
Hardware-aware motion estimation search algorithm development for high-efficiency video coding (HEVC) standard. ICIP 2012: 1529-1532 - [c4]Mahmut E. Sinangil, Anantha P. Chandrakasan, Vivienne Sze, Minhua Zhou:
Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine. ICIP 2012: 1533-1536 - 2011
- [j4]Masood Qazi, Mahmut E. Sinangil, Anantha P. Chandrakasan:
Challenges and Directions for Low-Voltage SRAM. IEEE Des. Test Comput. 28(1): 32-43 (2011) - [c3]Gordon Gammie, Nathan Ickes, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko:
A 28nm 0.6V low-power DSP for mobile applications. ISSCC 2011: 132-134 - [c2]Mahmut E. Sinangil, Hugh Mair, Anantha P. Chandrakasan:
A 28nm high-density 6T SRAM with optimized peripheral-assist circuits for operation down to 0.6V. ISSCC 2011: 260-262 - 2010
- [j3]Anantha P. Chandrakasan, Denis C. Daly, Daniel F. Finchelstein, Joyce Kwong, Yogesh K. Ramadass, Mahmut E. Sinangil, Vivienne Sze, Naveen Verma:
Technologies for Ultradynamic Voltage Scaling. Proc. IEEE 98(2): 191-214 (2010)
2000 – 2009
- 2009
- [j2]Vivienne Sze, Daniel F. Finchelstein, Mahmut E. Sinangil, Anantha P. Chandrakasan:
A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder. IEEE J. Solid State Circuits 44(11): 2943-2956 (2009) - [j1]Mahmut E. Sinangil, Naveen Verma, Anantha P. Chandrakasan:
A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS. IEEE J. Solid State Circuits 44(11): 3163-3173 (2009) - 2008
- [c1]Mahmut E. Sinangil, Naveen Verma, Anantha P. Chandrakasan:
A reconfigurable 65nm SRAM achieving voltage scalability from 0.25-1.2V and performance scalability from 20kHz-200MHz. ESSCIRC 2008: 282-285
Coauthor Index
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