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John K. DeBrosse
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2010 – 2019
- 2015
- [c1]John K. DeBrosse, Thomas M. Maffitt, Yutaka Nakamura, Guenole Jan, Po-Kang Wang:
A fully-functional 90nm 8Mb STT MRAM demonstrator featuring trimmed, reference cell-based sensing. CICC 2015: 1-3
2000 – 2009
- 2006
- [j10]Thomas M. Maffitt, John K. DeBrosse, John A. Gabric, Earl T. Gow, Mark C. Lamorey, John S. Parenteau, Dennis R. Willmott, Mark A. Wood, William J. Gallagher:
Design considerations for MRAM. IBM J. Res. Dev. 50(1): 25-40 (2006) - 2005
- [j9]Dietmar Gogl, Christian Arndt, John C. Barwin, Alexander Bette, John K. DeBrosse, Earl T. Gow, Heinz Hoenigschmid, Stefan Lammers, Mark C. Lamorey, Yu Lu, Tom Maffitt, Kim Maloney, Werner Obermaier, Andre Sturm, Hans Viehmann, Dennis R. Willmott, Mark A. Wood, William J. Gallagher, Gerhard Mueller, Arkalgud R. Sitaram:
A 16-Mb MRAM featuring bootstrapped write drivers. IEEE J. Solid State Circuits 40(4): 902-908 (2005) - 2004
- [j8]John K. DeBrosse, Dietmar Gogl, Alexander Bette, Heinz Hoenigschmid, Raphael Robertazzi, Christian Arndt, Daniel Braun, D. Casarotto, Robert Havreluk, Stefan Lammers, Werner Obermaier, William R. Reohr, Hans Viehmann, William J. Gallagher, Gerhard Müller:
A high-speed 128-kb MRAM core for future universal memory applications. IEEE J. Solid State Circuits 39(4): 678-683 (2004) - 2002
- [j7]Jack A. Mandelman, Robert H. Dennard, Gary B. Bronner, John K. DeBrosse, Rama Divakaruni, Yujun Li, Carl J. Raden:
Challenges and future directions for the scaling of dynamic random-access memory (DRAM). IBM J. Res. Dev. 46(2-3): 187-222 (2002) - 2000
- [j6]Heinz Hoenigschmid, Alexander Frey, John K. DeBrosse, Toshiaki Kirihata, Gerhard Mueller, Daniel W. Storaska, Gabriel Daniel, Gerd Frankowsky, Kevin P. Guay, David R. Hanson, Louis Lu-Chen Hsu, Brian Ji, Dmitry G. Netis, Steve Panaroni, Carl Radens, Armin M. Reith, Hartmud Terletzki, Oliver Weinfurtner, Johann Alsmeier, Werner Weber, Matthew R. Wordeman:
A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs. IEEE J. Solid State Circuits 35(5): 713-718 (2000)
1990 – 1999
- 1998
- [j5]Toshiaki Kirihata, Martin Gall, Kohji Hosokawa
, Jean-Marc Dortu, Hing Wong, Peter Pfefferl, Brian L. Ji, Oliver Weinfurtner, John K. DeBrosse, Hartmud Terletzki, Manfred Selz, Wayne Ellis, Matthew R. Wordeman, Oliver Kiehl:
A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture. IEEE J. Solid State Circuits 33(11): 1711-1719 (1998) - 1997
- [j4]Toshiaki Kirihata, Hing Wong, John K. DeBrosse, Yohji Watanabe, Takahiko Hara, Munehiro Yoshida, Matthew R. Wordeman, Shuso Fujii, Yoshiaki Asao, Bo Krsnik:
Flexible test mode approach for 256-Mb DRAM. IEEE J. Solid State Circuits 32(10): 1525-1534 (1997) - 1996
- [j3]Toshiaki Kirihata, Yohji Watanabe, Hing Wong, John K. DeBrosse, Munehiro Yoshida, Daisuke Kato, Shuso Fujii, Matthew R. Wordeman, Peter Poechmueller, Stephen A. Parke
Fault-tolerant designs for 256 Mb DRAM. IEEE J. Solid State Circuits 31(4): 558-566 (1996) - [j2]Yohji Watanabe, Ring Wong, Toshiaki Kirihata, Daisuke Kato, John K. DeBrosse, Takahiko Rara, Munehiro Yoshida, Rideo Mukai, Khandker N. Quader, Takeshi Nagai, Peter Poechmueller, Peter Pfefferl, Matthew R. Wordeman, Shuso Fujii:
A 286 mm2 256 Mb DRAM with ×32 both-ends DQ. IEEE J. Solid State Circuits 31(4): 567-574 (1996) - 1995
- [j1]Eric Adler, John K. DeBrosse, Stephen F. Geissler, Steven J. Holmes, Mark D. Jaffe, Jeffrey B. Johnson, Charles W. Koburger III, Jerome B. Lasky, Brian Lloyd, Glen L. Miles, James S. Nakos, Wendell P. Noble Jr., Steven H. Voldman, Michael Armacost, Richard Ferguson:
The evolution of IBM CMOS DRAM technology. IBM J. Res. Dev. 39(1-2): 167-188 (1995)
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