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Mark A. Indovina
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2020 – today
- 2024
- [j4]Sathwika Bavikadi
, Purab Ranjan Sutradhar
ReApprox-PIM: Reconfigurable Approximate Lookup-Table (LUT)-Based Processing-in-Memory (PIM) Machine Learning Accelerator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(8): 2288-2300 (2024) - [j3]Purab Ranjan Sutradhar
3DL-PIM: A Look-Up Table Oriented Programmable Processing in Memory Architecture Based on the 3-D Stacked Memory for Data-Intensive Applications. IEEE Trans. Emerg. Top. Comput. 12(1): 60-72 (2024) - 2023
- [c10]Purab Ranjan Sutradhar
FlutPIM: : A Look-up Table-based Processing in Memory Architecture with Floating-point Computation Support for Deep Learning Applications. ACM Great Lakes Symposium on VLSI 2023: 207-211 - [c9]Christie Agbalessi, Mark A. Indovina:
CNNET: A Configurable Hardware Accelerator for Efficient Inference of 8-bit Fixed-Point CNNs. SOCC 2023: 1-6 - 2022
- [j2]Purab Ranjan Sutradhar
Look-up-Table Based Processing-in-Memory Architecture With Programmable Precision-Scaling for Deep Learning Applications. IEEE Trans. Parallel Distributed Syst. 33(2): 263-275 (2022) - [c8]Sathwika Bavikadi
POLAR: Performance-aware On-device Learning Capable Programmable Processing-in-Memory Architecture for Low-Power ML Applications. DSD 2022: 889-898 - [c7]Prangon Das, Purab Ranjan Sutradhar, Mark A. Indovina, Sai Manoj Pudukotai Dinakarrao, Amlan Ganguly:
Implementation and Evaluation of Deep Neural Networks in Commercially Available Processing in Memory Hardware. SOCC 2022: 1-6 - 2021
- [c6]Mark Connolly, Purab Ranjan Sutradhar
Flexible Instruction Set Architecture for Programmable Look-up Table based Processing-in-Memory. ICCD 2021: 66-73 - 2020
- [j1]Purab Ranjan Sutradhar
pPIM: A Programmable Processor-in-Memory Architecture With Precision-Scaling for Deep Learning. IEEE Comput. Archit. Lett. 19(2): 118-121 (2020) - [c5]Rohini J. Gillela, Amlan Ganguly, Dorin Patru, Mark A. Indovina:
The IANET Hardware Accelerator for Audio and Visual Data Classification. SoCC 2020: 48-53
2010 – 2019
- 2018
- [c4]Tanmay Shinde, Suryanarayanan Subramaniam, Padmanabh Deshmukh, M. Meraj Ahmed, Mark A. Indovina, Amlan Ganguly:
A 0.24pJ/bit, 16Gbps OOK Transmitter Circuit in 45-nm CMOS for Inter and Intra-Chip Wireless Interconnects. ACM Great Lakes Symposium on VLSI 2018: 69-74 - [c3]Abhishek Vashist, Amlan Ganguly, Mark A. Indovina:
Testing WiNoC-Enabled Multicore Chips with BIST for Wireless Interconnects. NOCS 2018: 4:1-4:8 - 2017
- [c2]Suryanarayanan Subramaniam, Tanmay Shinde, Padmanabh Deshmukh, Md Shahriar Shamim, Mark A. Indovina
A 0.36pJ/bit, 17Gbps OOK receiver in 45-nm CMOS for inter and intra-chip wireless interconnects. SoCC 2017: 132-137
2000 – 2009
- 2006
- [c1]Christopher K. Lennard, Victor Berman, Saverio Fazzari, Mark A. Indovina
Industrially proving the SPIRIT consortium specifications for design chain integration. DATE Designers' Forum 2006: 142-147
Coauthor Index
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