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Bingjun Xiao
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2010 – 2019
- 2016
- [j2]Jason Cong, Peng Li
, Bingjun Xiao, Peng Zhang:
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(3): 407-418 (2016) - [c17]Bingjun Xiao, Jinjun Xiong
Novel applications of deep learning hidden features for adaptive testing. ASP-DAC 2016: 743-748 - [i1]Yu-Ting Chen, Jason Cong, Zhenman Fang, Bingjun Xiao, Peipei Zhou:
ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architectures. CoRR abs/1610.09761 (2016) - 2015
- [b2]Bingjun Xiao:
Communication Optimization for Customizable Domain-Specific Computing. University of California, Los Angeles, USA, 2015 - [b1]Yu-Ting Chen, Jason Cong, Michael Gill, Glenn Reinman, Bingjun Xiao:
Customizable Computing. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2015, ISBN 978-3-031-00620-3 - [c16]Peng Zhang, Muhuan Huang, Bingjun Xiao, Hui Huang, Jason Cong:
CMOST: a system-level FPGA compilation framework. DAC 2015: 158:1-158:6 - [c15]Chen Zhang
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks. FPGA 2015: 161-170 - [c14]Yu-Ting Chen, Jason Cong, Bingjun Xiao:
ARACompiler: a prototyping flow and evaluation framework for accelerator-rich architectures. ISPASS 2015: 157-158 - 2014
- [j1]Jason Cong, Bingjun Xiao:
FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 864-877 (2014) - [c13]Jason Cong, Peng Li
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Non-Uniform Partitioning of Data Reuse Buffers. DAC 2014: 77:1-77:6 - [c12]Jason Cong, Hui Huang, Chiyuan Ma, Bingjun Xiao, Peipei Zhou
A Fully Pipelined and Dynamically Composable Architecture of CGRA. FCCM 2014: 9-16 - [c11]Jason Cong, Bingjun Xiao:
Minimizing Computation in Convolutional Neural Networks. ICANN 2014: 281-290 - 2013
- [c10]Jason Cong, Guojie Luo, Kalliopi Tsota, Bingjun Xiao:
Optimizing routability in large-scale mixed-size placement. ASP-DAC 2013: 441-446 - [c9]Jason Cong, Bingjun Xiao:
Defect tolerance in nanodevice-based programmable interconnects: utilization beyond avoidance. DAC 2013: 9:1-9:8 - [c8]Jason Cong, Bingjun Xiao:
Defect recovery in nanodevice-based programmable interconnects (abstract only). FPGA 2013: 277-278 - [c7]Jason Cong, Bingjun Xiao:
Optimization of interconnects between accelerators and shared memories in dark silicon. ICCAD 2013: 630-637 - [c6]Yu-Ting Chen, Jason Cong, Mohammad Ali Ghodrat, Muhuan Huang, Chunyue Liu, Bingjun Xiao, Yi Zou:
Accelerator-rich CMPs: From concept to real hardware. ICCD 2013: 169-176 - [c5]Jason Cong, Milos D. Ercegovac, Muhuan Huang, Sen Li, Bingjun Xiao:
Energy-efficient computing using adaptive table lookup based on nonvolatile memories. ISLPED 2013: 280-285 - 2012
- [c4]Jason Cong, Bingjun Xiao:
FPGA-RR: an enhanced FPGA architecture with RRAM-based reconfigurable interconnects (abstract only). FPGA 2012: 268 - 2011
- [c3]Jason Cong, Karthik Gururaj, Muhuan Huang, Sen Li, Bingjun Xiao, Yi Zou:
Domain-specific processor with 3D integration for medical image processing. ASAP 2011: 247-250 - [c2]Jason Cong, Bingjun Xiao:
mrFPGA: A novel FPGA architecture with memristor-based reconfiguration. NANOARCH 2011: 1-8 - 2010
- [c1]Bingjun Xiao, Yiyu Shi, Lei He:
A universal state-of-charge algorithm for batteries. DAC 2010: 687-692
Coauthor Index
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