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Yijin Guan
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2020 – today
- 2024
- [c10]Teng Ma, Zheng Liu, Chengkun Wei, Jialiang Huang, Youwei Zhuo, Haoyu Li, Ning Zhang, Yijin Guan, Dimin Niu, Mingxing Zhang, Tao Ma:
HydraRPC: RPC in the CXL Era. USENIX ATC 2024: 387-395 - 2022
- [j6]Linyong Huang
, Zhe Zhang, Shuangchen Li, Dimin Niu
Practical Near-Data-Processing Architecture for Large-Scale Distributed Graph Neural Network. IEEE Access 10: 46796-46807 (2022) - [j5]Zhaoyang Du
Accelerating CPU-Based Sparse General Matrix Multiplication With Binary Row Merging. IEEE Access 10: 79237-79248 (2022) - [j4]Zhaoyang Du
OpSparse: A Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs. IEEE Access 10: 85960-85974 (2022) - [j3]Xingchen Li
Flatfish: A Reinforcement Learning Approach for Application-Aware Address Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4758-4770 (2022) - [j2]Qilin Zheng
PIMulator-NN: An Event-Driven, Cross-Level Simulation Framework for Processing-In-Memory-Based Neural Network Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5464-5475 (2022) - [c9]Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie:
Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio. ICPADS 2022: 483-490 - [c8]Shuangchen Li, Dimin Niu, Yuhao Wang, Wei Han, Zhe Zhang, Tianchan Guan, Yijin Guan, Heng Liu, Linyong Huang, Zhaoyang Du
Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network. ISCA 2022: 946-961 - [c7]Dimin Niu, Shuangchen Li, Yuhao Wang, Wei Han, Zhe Zhang, Yijin Guan, Tianchan Guan, Fei Sun, Fei Xue, Lide Duan, Yuanwei Fang, Hongzhong Zheng, Xiping Jiang, Song Wang, Fengguo Zuo, Yubing Wang, Bing Yu, Qiwei Ren, Yuan Xie:
184QPS/W 64Mb/mm23D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System. ISSCC 2022: 1-3 - [i4]Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Hongzhong Zheng, Yuan Xie:
Accelerating CPU-based Sparse General Matrix Multiplication with Binary Row Merging. CoRR abs/2206.06611 (2022) - [i3]Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Linyong Huang, Hongzhong Zheng, Yuan Xie:
OpSparse: a Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs. CoRR abs/2206.07244 (2022) - [i2]Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie:
Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio. CoRR abs/2207.13848 (2022) - 2021
- [c6]Zhe Zhou
BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices. DAC 2021: 1009-1014 - [i1]Zhe Zhou, Bizhao Shi
BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices. CoRR abs/2104.06214 (2021) - 2020
- [j1]Yijin Guan
Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs. IEEE Trans. Computers 69(7): 931-943 (2020) - [c5]Zhao Wang, Yijin Guan, Guangyu Sun, Dimin Niu, Yuhao Wang, Hongzhong Zheng, Yinhe Han:
GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks. ACA 2020: 73-86
2010 – 2019
- 2017
- [c4]Yijin Guan, Ningyi Xu, Chen Zhang
Using Data Compression for Optimizing FPGA-Based Convolutional Neural Network Accelerators. APPT 2017: 14-26 - [c3]Yijin Guan, Zhihang Yuan, Guangyu Sun, Jason Cong:
FPGA-based accelerator for long short-term memory recurrent neural networks. ASP-DAC 2017: 629-634 - [c2]Yijin Guan, Hao Liang, Ningyi Xu, Wenqiang Wang, Shaoshuai Shi, Xi Chen, Guangyu Sun, Wei Zhang, Jason Cong:
FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates. FCCM 2017: 152-159 - 2015
- [c1]Chen Zhang
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks. FPGA 2015: 161-170
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