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Jun-Hyeok Yang
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2020 – today
- 2024
- [j2]Jeong-Hyun Cho
, Hong-Hyun Bae
A Fully Integrated Multi-Phase Voltage Regulator With Flying-Capacitor-Based Inter-Inductor Current Self-Balancing Scheme and Charge-Recycling Gate Driver. IEEE J. Solid State Circuits 59(8): 2529-2544 (2024) - [c6]Hong-Hyun Bae, Jeong-Hyun Cho, Kihyun Kim, Seunghwa Shin, Doojin Jang, Jun-Hyeok Yang, Hyun-Sik Kim:
A 7V/μs-DVS Class-G Digital-Shunt-Aided Buck Voltage Regulator Achieving a 7% Dynamic-Efficiency Drop at a 600kHz DVS Occurrence Frequency in 28nm CMOS. CICC 2024: 1-2 - [c5]Hyo-Jin Park, Joo-Mi Cho, Chan-Ho Lee, Young-Ju Oh, Hyunwoo Jeong, Jun-Hyeok Yang, Jaeseung Lee, Sung-Wan Hong:
8.8 A 97.18% Peak-Efficiency Asymmetrically Implemented Dual-phase (AID) Converter with a full Voltage-Conversion Ratio (VCR) between 0-and-1. ISSCC 2024: 1-3 - 2022
- [j1]Jun-Hwan Jang
A 0.5-1 V, -68 dB Power Supply Rejection Capacitorless Analog LDO Using Voltage-to-Time Conversion in 28-nm CMOS. IEEE J. Solid State Circuits 57(8): 2462-2473 (2022) - [c4]Woojoong Jung, Minsu Kim, Hyunjun Park, Sungmin Yoo, Tae-Hwang Kong, Jun-Hyeok Yang, Michael Choi, Jongshin Shin, Hyung-Min Lee
A Hybrid Always-Dual-Path Recursive Step-Down Converter Using Adaptive Switching Level Control Achieving 95.4% Efficiency with 288mΩ Large-DCR Inductor. CICC 2022: 1-2 - [c3]Junghyun Park, Jooseong Kim, Kwangho Kim, Jun-Hyeok Yang, Michael Choi, Jongshin Shin:
A 0.65V 1316µm2Fully Synthesizable Digital Temperature Sensor Using Wire Metal Achieving O.16nJ.%2-Accuracy FoM in 5nm FinFET CMOS. ISSCC 2022: 220-222 - [c2]Jeong-Hyun Cho, Hong-Hyun Bae, Gyu-Wan Lim, Tae-Hwang Kong, Jun-Hyeok Yang, Hyun-Sik Kim:
A Fully-Integrated 0.9W/mm2 79.1%-Efficiency 200MHz Multi-Phase Buck Converter with Flying-Capacitor-Based Inter-Inductor Current Balancing Technique. VLSI Technology and Circuits 2022: 196-197 - 2021
- [c1]Dong-Hoon Jung, Tae-Hwang Kong, Jun-Hyeok Yang, SangHo Kim, Kwangho Kim, Jeongpyo Park, Michael Choi, Jongshin Shin:
29.6 A Distributed Digital LDO with Time-Multiplexing Calibration Loop Achieving 40A/mm2 Current Density and 1mA-to-6.4A Ultra-Wide Load Range in 5nm FinFET CMOS. ISSCC 2021: 414-416
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