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Eero Aho
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2010 – 2019
- 2012
- [c9]Eero Aho, Kimmo Kuusilinna, Tomi Aarnio, Janne Pietiainen, Jari Nikara:
Towards real-time applications in mobile web browsers. ESTIMedia 2012: 57-66 - 2011
- [c8]Claudio Brunelli, Eero Aho, Heikki Berg:
OpenCL implementation of Cholesky matrix decomposition. SoC 2011: 62-67
2000 – 2009
- 2009
- [j8]Jarno Vanne
, Eero Aho, Kimmo Kuusilinna, Timo D. Hämäläinen:
A Configurable Motion Estimation Architecture for Block-Matching Algorithms. IEEE Trans. Circuits Syst. Video Technol. 19(4): 466-477 (2009) - [c7]Eero Aho, Jari Nikara, Petri A. Tuominen, Kimmo Kuusilinna:
A case for multi-channel memories in video recording. DATE 2009: 934-939 - [c6]Jari Nikara, Eero Aho, Petri A. Tuominen, Kimmo Kuusilinna:
Performance analysis of multi-channel memories in mobile devices. SoC 2009: 128-131 - [c5]Eero Aho, Kimmo Kuusilinna, Jari Nikara:
Memory access characteristics of H.264 video encoder on embedded processor. SiPS 2009: 255-260 - 2008
- [j7]Jarno Vanne
A Parallel Memory System for Variable Block-Size Motion Estimation Algorithms. IEEE Trans. Circuits Syst. Video Technol. 18(4): 538-543 (2008) - [j6]Eero Aho, Jarno Vanne
Configurable Data Memory for Multimedia Processing. J. Signal Process. Syst. 50(2): 231-249 (2008) - 2007
- [j5]Eero Aho, Jarno Vanne
Configurable implementation of parallel memory based real-time video downscaler. Microprocess. Microsystems 31(5): 283-292 (2007) - 2006
- [j4]Jarno Vanne
A High-Performance Sum of Absolute Difference Implementation for Motion Estimation. IEEE Trans. Circuits Syst. Video Technol. 16(7): 876-883 (2006) - [c4]Eero Aho, Jarno Vanne
Parallel Memory Architecture for Arbitrary Stride Accesses. DDECS 2006: 65-70 - [c3]Eero Aho, Jarno Vanne
Parallel Memory Implementation for Arbitrary Stride Accesses. ICSAMOS 2006: 1-6 - 2005
- [j3]Eero Aho, Jarno Vanne
Block-level parallel processing for scaling evenly divisible images. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(12): 2717-2725 (2005) - [j2]Eero Aho, Jarno Vanne
Comments on "Winscale: an image-scaling algorithm using an area pixel Model". IEEE Trans. Circuits Syst. Video Technol. 15(3): 454-455 (2005) - [c2]Eero Aho, Jarno Vanne
Block-level parallel processing for scaling evenly divisible frames. ISCAS (2) 2005: 1134-1137 - 2004
- [j1]Eero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo D. Hämäläinen:
Address Computation in Configurable Parallel Memory Architecture. IEICE Trans. Inf. Syst. 87-D(7): 1674-1681 (2004) - 2002
- [c1]Jarno Vanne
Enhanced Configurable Parallel Memory Architecture. DSD 2002: 28-37
Coauthor Index
aka: Timo D. Hämäläinen
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