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Jyotishman Saikia
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2020 – today
- 2024
- [j4]Bo Zhang
, Jyotishman Saikia, Jian Meng
MACC-SRAM: A Multistep Accumulation Capacitor-Coupling In-Memory Computing SRAM Macro for Deep Convolutional Neural Networks. IEEE J. Solid State Circuits 59(6): 1938-1949 (2024) - 2023
- [j3]Bo Zhang
PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference. IEEE J. Solid State Circuits 58(5): 1436-1449 (2023) - [j2]Shreyas Kolala Venkataramanaiah, Jian Meng
A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity. IEEE J. Solid State Circuits 58(7): 1885-1897 (2023) - [c7]Jyotishman Saikia, Amitesh Sridharan, Injune Yeo
FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro. ESSCIRC 2023: 405-408 - 2022
- [c6]Bo Zhang, Jyotishman Saikia, Jian Meng, Dewei Wang, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-sun Seo, Mingoo Seok:
A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks. CICC 2022: 1-2 - [c5]Shreyas Kolala Venkataramanaiah, Jian Meng, Han-Sok Suh, Injune Yeo
A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification. ESSCIRC 2022: 89-92 - 2021
- [c4]Jyotishman Saikia, Shihui Yin, Sai Kiran Cherupally, Bo Zhang, Jian Meng, Mingoo Seok, Jae-Sun Seo:
Modeling and Optimization of SRAM-based In-Memory Computing Hardware Design. DATE 2021: 942-947 - [c3]Shihui Yin, Bo Zhang, Minkyu Kim, Jyotishman Saikia, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Mingoo Seok, Jae-sun Seo:
PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference. VLSI Circuits 2021: 1-2
2010 – 2019
- 2019
- [c2]Jyotishman Saikia, Shihui Yin, Zhewei Jiang, Mingoo Seok, Jae-sun Seo:
K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM. ISLPED 2019: 1-6 - 2018
- [j1]Sandeep Mishra
A Low-Overhead Dynamic TCAM With Pipelined Read-Restore Refresh Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(5): 1591-1601 (2018) - 2017
- [c1]Venkatesh Mani Tripathi, Sandeep Mishra
A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access. VLSID 2017: 341-346
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