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Shihui Yin
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2020 – today
- 2023
- [j12]Bo Zhang
, Shihui Yin
PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference. IEEE J. Solid State Circuits 58(5): 1436-1449 (2023) - 2022
- [j11]Sai Kiran Cherupally
Improving DNN Hardware Accuracy by In-Memory Computing Noise Injection. IEEE Des. Test 39(4): 71-80 (2022) - [j10]Xiaocong Du
Efficient continual learning at the edge with progressive segmented training. Neuromorph. Comput. Eng. 2(4): 44006 (2022) - [c30]Kailiang Huang, Xinlv Duan, Junxiao Feng, Ying Sun, Congyan Lu, Chuanke Chen, Guangfan Jiao, Xinpeng Lin, Jinhai Shao, Shihui Yin, Jiazhen Sheng
Vertical Channel-All-Around (CAA) IGZO FET under 50 nm CD with High Read Current of 32.8 μA/μm (Vth + 1 V), Well-performed Thermal Stability up to 120 ℃ for Low Latency, High-density 2T0C 3D DRAM Application. VLSI Technology and Circuits 2022: 296-297 - [c29]Jingrui Guo, Ying Sun, Lingfei Wang, Xinlv Duan, Kailiang Huang, Zhaogui Wang, Junxiao Feng, Qian Chen, Shijie Huang, Lihua Xu, Di Geng, Guangfan Jiao, Shihui Yin, Zhengbo Wang, Weiliang Jing, Ling Li, Ming Liu:
Compact Modeling of IGZO-based CAA-FETs with Time-zero-instability and BTI Impact on Device and Capacitor-less DRAM Retention Reliability. VLSI Technology and Circuits 2022: 300-301 - 2021
- [c28]Sai Kiran Cherupally, Adnan Siraj Rakin, Shihui Yin, Mingoo Seok, Deliang Fan, Jae-sun Seo:
Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robust DNN Hardware Against Adversarial Input and Weight Attacks. DAC 2021: 559-564 - [c27]Jyotishman Saikia, Shihui Yin, Sai Kiran Cherupally, Bo Zhang, Jian Meng, Mingoo Seok, Jae-Sun Seo:
Modeling and Optimization of SRAM-based In-Memory Computing Hardware Design. DATE 2021: 942-947 - [c26]Wangxin He, Wonbo Shim, Shihui Yin, Xiaoyu Sun, Deliang Fan, Shimeng Yu
Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing. IRPS 2021: 1-7 - [c25]Shihui Yin, Bo Zhang, Minkyu Kim, Jyotishman Saikia, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Mingoo Seok, Jae-sun Seo:
PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference. VLSI Circuits 2021: 1-2 - 2020
- [b1]Shihui Yin:
Energy-Efficient Circuit and Architecture Designs for Intelligent Systems. Arizona State University, Tempe, USA, 2020 - [j9]Shihui Yin
XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks. IEEE J. Solid State Circuits 55(6): 1733-1743 (2020) - [j8]Deepak Kadetotad, Shihui Yin
An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition. IEEE J. Solid State Circuits 55(7): 1877-1887 (2020) - [j7]Zhewei Jiang
C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism. IEEE J. Solid State Circuits 55(7): 1888-1897 (2020) - [j6]Sai Kiran Cherupally
A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation. IEEE J. Solid State Circuits 55(10): 2680-2690 (2020) - [j5]Sai Kiran Cherupally
ECG Authentication Hardware Design With Low-Power Signal Processing and Neural Network Optimization With Low Precision and Structured Compression. IEEE Trans. Biomed. Circuits Syst. 14(2): 198-208 (2020) - [j4]Shihui Yin
Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. 28(1): 48-61 (2020) - [c24]Shruti R. Kulkarni, Shihui Yin, Jae-sun Seo, Bipin Rajendran:
An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays. DATE 2020: 1019-1024 - [c23]Shreyas K. Venkataramanaiah, Han-Sok Suh, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao
FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory. ICCAD 2020: 74:1-74:8 - [c22]Shreyas Kolala Venkataramanaiah, Xiaocong Du, Zheng Li, Shihui Yin, Yu Cao, Jae-sun Seo:
Efficient and Modularized Training on FPGA for Real-time Applications. IJCAI 2020: 5237-5239 - [c21]Shreyas K. Venkataramanaiah, Shihui Yin, Yu Cao, Jae-Sun Seo:
Deep Neural Network Training Accelerator Designs in ASIC and FPGA. ISOCC 2020: 21-22
2010 – 2019
- 2019
- [j3]Shihui Yin
A 1.06- $\mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring. IEEE J. Solid State Circuits 54(8): 2316-2326 (2019) - [j2]Shihui Yin, Jae-sun Seo, Yulhwa Kim
Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning. IEEE Micro 39(6): 54-63 (2019) - [c20]Zhewei Jiang, Shihui Yin, Minkyu Kim, Tushar Gupta, Mingoo Seok, Jae-sun Seo:
Vesti: An In-Memory Computing Processor for Deep Neural Networks Acceleration. ACSSC 2019: 1516-1521 - [c19]Sai Kiran Cherupally, Shihui Yin, Deepak Kadetotad, Chisung Bae, Sang Joon Kim, Jae-Sun Seo:
A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV and SRAM PUF for Authentication and Secret Key Generation. A-SSCC 2019: 145-148 - [c18]Zhewei Jiang, Shihui Yin, Jae-Sun Seo, Mingoo Seok:
C3SRAM: In-Memory-Computing SRAM Macro Based on Capacitive-Coupling Computing. ESSCIRC 2019: 131-134 - [c17]Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao
Automatic Compiler Based FPGA Accelerator for CNN Training. FPL 2019: 166-172 - [c16]Zhewei Jiang, Shihui Yin, Jae-sun Seo, Mingoo Seok:
XNOR-SRAM: In-Bitcell Computing SRAM Macro based on Resistive Computing Mechanism. ACM Great Lakes Symposium on VLSI 2019: 417-422 - [c15]Gaurav Srivastava
Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks. ICASSP 2019: 1393-1397 - [c14]Shruti R. Kulkarni, Deepak Vinayak Kadetotad, Shihui Yin, Jae-Sun Seo, Bipin Rajendran:
Neuromorphic Hardware Accelerator for SNN Inference based on STT-RAM Crossbar Arrays. ICECS 2019: 438-441 - [c13]Sai Kiran Cherupally, Gaurav Srivastava
ECG Authentication Neural Network Hardware Design with Collective Optimization of Low Precision and Structured Compression. ISCAS 2019: 1-5 - [c12]Jyotishman Saikia, Shihui Yin, Zhewei Jiang, Mingoo Seok, Jae-sun Seo:
K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM. ISLPED 2019: 1-6 - [c11]Xiaochen Peng, Minkyu Kim, Xiaoyu Sun, Shihui Yin, Titash Rakshit, Ryan M. Hatcher, Jorge A. Kittl, Jae-sun Seo, Shimeng Yu
Inference engine benchmarking across technological platforms from CMOS to RRAM. MEMSYS 2019: 471-479 - [i4]Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo:
Automatic Compiler Based FPGA Accelerator for CNN Training. CoRR abs/1908.06724 (2019) - [i3]Shihui Yin, Xiaoyu Sun, Shimeng Yu, Jae-sun Seo:
High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS. CoRR abs/1909.07514 (2019) - 2018
- [j1]Minhee Jun, Rohit Negi, Shihui Yin, Mohamed Baker Alawieh
Environment-Adaptable Fast Multi-Resolution (EAF-MR) optimization in large-scale RF-FPGA systems. EURASIP J. Wirel. Commun. Netw. 2018: 68 (2018) - [c10]Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo, Shimeng Yu
XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks. DATE 2018: 1423-1428 - [c9]Shihui Yin, Xiaoyu Sun, Shimeng Yu
A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks. SiPS 2018: 13-18 - [i2]Shihui Yin, Gaurav Srivastava, Shreyas K. Venkataramanaiah, Chaitali Chakrabarti, Visar Berisha, Jae-sun Seo:
Minimizing Area and Energy of Deep Learning Hardware Design Using Collective Low Precision and Structured Compression. CoRR abs/1804.07370 (2018) - 2017
- [c8]Shihui Yin, Gaurav Srivastava
Minimizing area and energy of deep learning hardware design using collective low precision and structured compression. ACSSC 2017: 1907-1911 - [c7]Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao
Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations. BioCAS 2017: 1-5 - [c6]Shihui Yin, Chisung Bae, Sang Joon Kim, Jae-sun Seo:
Designing ECG-based physical unclonable function for security of wearable devices. EMBC 2017: 3509-3512 - [c5]Mohamed Baker Alawieh
Efficient programming of reconfigurable radio frequency (RF) systems. ICCAD 2017: 772-779 - [i1]Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, Jae-sun Seo:
Algorithm and Hardware Design of Discrete-Time Spiking Neural Networks Based on Back Propagation with Binary Activations. CoRR abs/1709.06206 (2017) - 2016
- [c4]Fa Wang, Shihui Yin, Minhee Jun, Xin Li, Tamal Mukherjee
Re-thinking polynomial optimization: Efficient programming of reconfigurable radio frequency (RF) systems by convexification. ASP-DAC 2016: 545-550 - 2015
- [c3]Ying-Chih Wang, Shihui Yin, Minhee Jun, Xin Li, Lawrence T. Pileggi, Tamal Mukherjee
Accurate passivity-enforced macromodeling for RF circuits via iterative zero/pole update based on measurement data. ASP-DAC 2015: 441-446 - [c2]Minhee Jun, Rohit Negi, Shihui Yin, Fa Wang, Megha Sunny, Tamal Mukherjee, Xin Li:
Phase Noise Impairment and Environment-Adaptable Fast (EAF) Optimization for Programming of Reconfigurable Radio Frequency (RF) Receivers. GLOBECOM 2015: 1-6 - 2014
- [c1]Minhee Jun, Rohit Negi, Jun Tao, Ying-Chih Wang, Shihui Yin, Tamal Mukherjee
Environment-Adaptable Efficient Optimization for Programming of Reconfigurable Radio Frequency (RF) Receivers. MILCOM 2014: 1459-1465
Coauthor Index
aka: Jae-Sun Seo
aka: Shreyas Kolala Venkataramanaiah
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