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Vacius Jusas
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2020 – today
- 2024
- [c16]Amr F. Mohamed
, Vacius Jusas
Comprehensive Analysis of Feature Extraction Methods for Emotion Recognition on Motor Imagery from Multichannel EEG Recordings. WorldCIST (2) 2024: 211-231 - 2021
- [j27]Zeba Mahmood, Vacius Jusas
Implementation Framework for a Blockchain-Based Federated Learning Model for Classification Problems. Symmetry 13(7): 1116 (2021) - 2020
- [j26]Sandeepak Bhandari, Vacius Jusas
An Abstraction Based Approach for Reconstruction of TimeLine in Digital Forensics. Symmetry 12(1): 104 (2020) - [j25]Sandeepak Bhandari
An Ontology Based on the Timeline of Log2timeline and Psort Using Abstraction Approach in Digital Forensics. Symmetry 12(4): 642 (2020) - [c15]Sandeepak Bhandari, Vacius Jusas
The Phases Based Approach for Regeneration of Timeline in Digital Forensics. INISTA 2020: 1-6
2010 – 2019
- 2019
- [j24]Vacius Jusas
Logical filter approach for early stage cyber-attack detection. Comput. Sci. Inf. Syst. 16(2): 491-514 (2019) - [j23]Vacius Jusas
Classification of Motor Imagery Using Combination of Feature Extraction and Reduction Methods for Brain-Computer Interface. Inf. Technol. Control. 48(2): 225-234 (2019) - [j22]Vacius Jusas, Jiaxu Zhang, Jing Li:
Robust Backstepping Sliding Mode Control with L2-Gain Performance for Reference Input Wheel Slip Tracking of Vehicle. Inf. Technol. Control. 48(4): 660-672 (2019) - 2018
- [j21]Eduardas Bareisa, Vacius Jusas
Black box delay fault models for non-scan sequential circuits. Comput. Sci. Inf. Syst. 15(1): 237-256 (2018) - [j20]Tomas Uktveris
Development of a Modular Board for EEG Signal Acquisition. Sensors 18(7): 2140 (2018) - 2017
- [j19]Vacius Jusas, Joaquín Nicolás Ros, Boriss Misnevs:
Software Engineering Competence Remote Evaluation Process Model. Balt. J. Mod. Comput. 5(3) (2017) - [j18]Algimantas Venckauskas
Methodology to investigate BitTorrent sync protocol. Comput. Sci. Inf. Syst. 14(1): 197-218 (2017) - [j17]Tomas Uktveris, Vacius Jusas
Application of Convolutional Neural Networks to Four-Class Motor Imagery Classification Problem. Inf. Technol. Control. 46(2): 260-273 (2017) - [j16]Vacius Jusas
Methods and Tools of Digital Triage in Forensic Context: Survey and Future Directions. Symmetry 9(4): 49 (2017) - [c14]Tomas Uktveris, Vacius Jusas
Convolutional Neural Networks for Four-Class Motor Imagery Data Classification. IDC 2017: 185-197 - 2016
- [j15]Algimantas Venckauskas
A Methodology and Tool for Investigation of Artifacts Left by the BitTorrent Client. Symmetry 8(6): 40 (2016) - 2015
- [j14]Darius Birvinskas, Vacius Jusas
Fast DCT algorithms for EEG data compression in embedded systems. Comput. Sci. Inf. Syst. 12(1): 49-62 (2015) - [j13]Eduardas Bareisa, Vacius Jusas
Path delay test generation at functional level. IET Comput. Digit. Tech. 9(3): 135-141 (2015) - [j12]Algimantas Venckauskas
Investigation of Artifacts Left by BitTorrent Client on the Local Computer Operating under Windows 8.1. Inf. Technol. Control. 44(4): 451-461 (2015) - [c13]Darius Birvinskas, Vacius Jusas
Energy Efficient Method for Motor Imagery Data Compression. ICIST 2015: 71-80 - [c12]Tomas Uktveris, Vacius Jusas
Comparison of Feature Extraction Methods for EEG BCI Classification. ICIST 2015: 81-92 - 2014
- [j11]Vacius Jusas
Stimuli generation framework for testing multiple processes in VHDL. Inf. Technol. Control. 43(4): 440-446 (2014) - [c11]Vacius Jusas
Stimuli generator for testing processes in VHDL. NORCHIP 2014: 1-4 - 2013
- [j10]Eduardas Bareisa, Vacius Jusas
Functional delay test generation approach using a software prototype of the circuit. Comput. Sci. Inf. Syst. 10(3): 1165-1184 (2013) - [j9]Darius Birvinskas, Vacius Jusas
Data compression of EEG signals for artificial neural network classification. Inf. Technol. Control. 42(3): 238-241 (2013) - [j8]Vacius Jusas
Combining Software and Hardware Test Generation Methods to Verify VHDL Models. Inf. Technol. Control. 42(4): 362-368 (2013) - [j7]Eduardas Bareisa, Vacius Jusas
Delay fault testing using partial multiple scan chains. Microelectron. Reliab. 53(12): 2070-2077 (2013) - [c10]Ignas Martisius, Darius Birvinskas, Robertas Damasevicius
EEG Dataset Reduction and Classification Using Wave Atom Transform. ICANN 2013: 208-215 - [c9]Vacius Jusas
Novel Method to Generate Tests for VHDL. ICIST 2013: 365-375 - 2012
- [j6]Eduardas Bareisa, Vacius Jusas
Evaluation of testability enhancement using software prototype. IET Comput. Digit. Tech. 6(3): 166-172 (2012) - [c8]Darius Birvinskas, Vacius Jusas
EEG Dataset Reduction and Feature Extraction Using Discrete Cosine Transform. EMS 2012: 199-204 - [c7]Vacius Jusas
FSM Based Functional Test Generation Framework for VHDL. ICIST 2012: 138-148 - 2011
- [j5]Eduardas Bareisa, Vacius Jusas
Functional fault models for non-scan sequential circuits. Microelectron. Reliab. 51(12): 2402-2411 (2011)
2000 – 2009
- 2009
- [j4]Eduardas Bareisa, Vacius Jusas
Functional delay test generation based on software prototype. Microelectron. Reliab. 49(12): 1578-1585 (2009) - 2008
- [j3]Eduardas Bareisa, Vacius Jusas
Test generation at the algorithm-level for gate-level fault coverage. Microelectron. Reliab. 48(7): 1093-1101 (2008) - [c6]Eduardas Bareisa, Vacius Jusas
Development of Functional Delay Tests. DSD 2008: 626-632 - 2007
- [j2]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
Functional Test Generation Based on Combined Random and Deterministic Search Methods. Informatica 18(1): 3-26 (2007) - [c5]Eduardas Bareisa, Vacius Jusas
Transition Faults Testing Based on Functional Delay Tests. DDECS 2007: 371-376 - [c4]Eduardas Bareisa, Vacius Jusas
The Criteria of Functional Delay Test Quality Assessment. DSD 2007: 207-214 - 2006
- [c3]Eduardas Bareisa, Vacius Jusas
Transition Fault Test Reuse. DSD 2006: 323-330 - 2005
- [j1]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
The Realization-Independent Testing Based on the Black Box Fault Models. Informatica 16(1): 19-36 (2005) - [c2]Eduardas Bareisa, Vacius Jusas
Functional Test Generation Remote Tool. DSD 2005: 192-195 - 2001
- [c1]Vacius Jusas, Kestutis Paulikas, Rimantas Seinauskas:
Procedures for Selection of Validation Vectors on the Algorithm Level. LATW 2001: 90-95
Coauthor Index
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