Abstract
The major challenge for the semiconductor industry is to design devices in short time with complex logical functionality. At the very top of the list of challenges to be solved is verification. The goal of the verification is to ensure that the design meets the logical functional requirements as defined in the logical functional specification. Verification of the devices takes 40 to 70 per cent of the total development effort for the design. The increasing complexity of hardware designs raises the need for the development of new techniques and methodologies that can provide the verification team with the means to achieve its goals quickly and with limited resources.
We present a framework that enables verification test generation using circuit model presented in VHDL hardware description language. The framework consists of several tools. We use the third party tool VSYML for VHDL description translation. Our tool then extracts finite state machine (FSM) model from translated VHDL description. The goal of the model is to use it for verification test generation. We introduce our software tool and algorithm, as well. The experimental results are presented for the benchmark suite ITC’99. The obtained results demonstrated the viability of the framework.
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Jusas, V., Neverdauskas, T. (2012). FSM Based Functional Test Generation Framework for VHDL. In: Skersys, T., Butleris, R., Butkiene, R. (eds) Information and Software Technologies. ICIST 2012. Communications in Computer and Information Science, vol 319. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-33308-8_12
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DOI: https://doi.org/10.1007/978-3-642-33308-8_12
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