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Yakun Sophia Shao
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2020 – today
- 2024
- [j11]Seah Kim
, Jerry Zhao
AuRORA: A Full-Stack Solution for Scalable and Virtualized Accelerator Integration. IEEE Micro 44(4): 97-105 (2024) - [c32]Yakun Sophia Shao:
Next-Generation Domain-Specific Accelerators: From Hardware to System. CICC 2024: 1-5 - [c31]Joonho Whangbo, Edwin Lim, Chengyi Lux Zhang, Kevin Anderson, Abraham Gonzalez, Raghav Gupta, Nivedha Krishnakumar, Sagar Karandikar, Borivoje Nikolic, Yakun Sophia Shao, Krste Asanovic:
FireAxe: Partitioned FPGA-Accelerated Simulation of Large-Scale RTL Designs. ISCA 2024: 501-515 - [c30]Vikram Jain
Design Approach for Die-to-Die Interfaces to Enable Energy-Efficient Chiplet Systems. ISLPED 2024: 1-6 - [i12]Coleman Hooper, Sehoon Kim, Hiva Mohammadzadeh, Michael W. Mahoney, Yakun Sophia Shao, Kurt Keutzer, Amir Gholami:
KVQuant: Towards 10 Million Context Length LLM Inference with KV Cache Quantization. CoRR abs/2401.18079 (2024) - [i11]Xiaoyu Huang, Yufeng Chi, Ruofeng Wang, Zhongyu Li, Xue Bin Peng, Yakun Sophia Shao, Borivoje Nikolic, Koushil Sreenath:
DiffuseLoco: Real-Time Legged Locomotion Control with Diffusion from Offline Datasets. CoRR abs/2404.19264 (2024) - [i10]Charles Hong, Sahil Bhatia, Altan Haan, Shengjun Kris Dong, Dima Nikiforov, Alvin Cheung, Yakun Sophia Shao:
LLM-Aided Compilation for Tensor Accelerators. CoRR abs/2408.03408 (2024) - [i9]Hansung Kim, Ruohan Yan, Joshua You, Tieliang Vamber Yang, Yakun Sophia Shao:
Virgo: Cluster-level Matrix Unit Integration in GPUs for Scalability and Energy Efficiency. CoRR abs/2408.12073 (2024) - 2023
- [j10]Masum Hossain, Arijit Raychowdhury, Sanu K. Mathew, Yakun Sophia Shao, Yih Wang:
Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 58(1): 3-7 (2023) - [c29]Seah Kim
MoCA: Memory-Centric, Adaptive Execution for Multi-Tenant Deep Neural Networks. HPCA 2023: 828-841 - [c28]Sagar Karandikar
CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems. ISCA 2023: 39:1-39:17 - [c27]Dima Nikiforov
RoSÉ: A Hardware-Software Co-Simulation Infrastructure Enabling Pre-Silicon Full-Stack Robotics SoC Evaluation. ISCA 2023: 64:1-64:15 - [c26]Seah Kim
AuRORA: Virtualized Accelerator Orchestration for Multi-Tenant Workloads. MICRO 2023: 62-76 - [c25]Charles Hong
DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators. MICRO 2023: 209-224 - [d1]Dima Nikiforov
RoSÉ: A Hardware-Software Co-Simulation Infrastructure Enabling Pre-Silicon Full-Stack Robotics SoC Evaluation. Zenodo, 2023 - [i8]Sehoon Kim, Coleman Hooper, Thanakul Wattanawong, Minwoo Kang, Ruohan Yan, Hasan Genc, Grace Dinh, Qijing Huang, Kurt Keutzer, Michael W. Mahoney, Yakun Sophia Shao, Amir Gholami:
Full Stack Optimization of Transformer Inference: a Survey. CoRR abs/2302.14017 (2023) - [i7]Seah Kim, Hasan Genc, Vadim Vadimovich Nikiforov, Krste Asanovic, Borivoje Nikolic, Yakun Sophia Shao:
MoCA: Memory-Centric, Adaptive Execution for Multi-Tenant Deep Neural Networks. CoRR abs/2305.05843 (2023) - [i6]Yuto Nishida, Sahil Bhatia, Shadaj Laddad, Hasan Genc, Yakun Sophia Shao, Alvin Cheung
Code Transpilation for Hardware Accelerators. CoRR abs/2308.06410 (2023) - [i5]Coleman Hooper, Sehoon Kim, Hiva Mohammadzadeh, Hasan Genc, Kurt Keutzer, Amir Gholami, Yakun Sophia Shao:
SPEED: Speculative Pipelined Execution for Efficient Decoding. CoRR abs/2310.12072 (2023) - 2022
- [j9]Alisha Menon
Efficient emotion recognition using hyperdimensional computing with combinatorial channel encoding and cellular automata. Brain Informatics 9(1): 14 (2022) - [c24]Qijing Huang
Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design. ISPASS 2022: 277-287 - 2021
- [j8]Yakun Sophia Shao, Jason Clemons
Simba: scaling deep-learning inference with chiplet-based architecture. Commun. ACM 64(6): 107-116 (2021) - [j7]Jie-Fang Zhang
SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference. IEEE J. Solid State Circuits 56(2): 636-647 (2021) - [c23]Hasan Genc, Seah Kim, Alon Amid, Ameer Haj-Ali, Vighnesh Iyer
Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration. DAC 2021: 769-774 - [c22]Abraham Gonzalez, Jerry Zhao, Ben Korpan, Hasan Genc, Colin Schmidt, John Charles Wright, Ayan Biswas, Alon Amid, Farhana Sheikh
A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET. ESSCIRC 2021: 259-262 - [c21]Qijing Huang
CoSA: Scheduling by Constrained Optimization for Spatial Accelerators. ISCA 2021: 554-566 - [c20]Alon Amid, Albert J. Ou, Krste Asanovic, Yakun Sophia Shao, Borivoje Nikolic
Vertically Integrated Computing Labs Using Open-Source Hardware Generators and Cloud-Hosted FPGAs. ISCAS 2021: 1-5 - [c19]Jingyi Xu, Sehoon Kim, Borivoje Nikolic
Memory-Efficient Hardware Performance Counters with Approximate-Counting Algorithms. ISPASS 2021: 226-228 - [i4]Alisha Menon, Anirudh Natarajan, Reva Agashe, Daniel Sun, Melvin Aristio, Harrison Liew, Yakun Sophia Shao, Jan M. Rabaey:
Efficient emotion recognition using hyperdimensional computing with combinatorial channel encoding and cellular automata. CoRR abs/2104.02804 (2021) - [i3]Qijing Huang, Minwoo Kang, Grace Dinh, Thomas Norell, Aravind Kalaiah, James Demmel, John Wawrzynek, Yakun Sophia Shao:
CoSA: Scheduling by Constrained Optimization for Spatial Accelerators. CoRR abs/2105.01898 (2021) - 2020
- [j6]Brian Zimmer
A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. IEEE J. Solid State Circuits 55(4): 920-932 (2020) - [j5]Alon Amid
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs. IEEE Micro 40(4): 10-21 (2020) - [j4]David A. Patterson, Yakun Sophia Shao:
Commercial Products. IEEE Micro 40(6): 49 (2020) - [c18]Ameer Haj-Ali, Nesreen K. Ahmed
NeuroVectorizer: end-to-end vectorization with deep reinforcement learning. CGO 2020: 242-255 - [c17]Alon Amid, David Biancolin, Abraham Gonzalez, Daniel Grubb, Sagar Karandikar, Harrison Liew
Invited: Chipyard - An Integrated SoC Research and Implementation Environment. DAC 2020: 1-6
2010 – 2019
- 2019
- [c16]Michael Pellauer, Yakun Sophia Shao, Jason Clemons, Neal Clayton Crago, Kartik Hegde, Rangharajan Venkatesan, Stephen W. Keckler, Christopher W. Fletcher, Joel S. Emer:
Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration. ASPLOS 2019: 137-151 - [c15]Rangharajan Venkatesan, Yakun Sophia Shao, Brian Zimmer, Jason Clemons
A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. Hot Chips Symposium 2019: 1-24 - [c14]Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang
MAGNet: A Modular Accelerator Generator for Neural Networks. ICCAD 2019: 1-8 - [c13]Angshuman Parashar, Priyanka Raina
Timeloop: A Systematic Approach to DNN Accelerator Evaluation. ISPASS 2019: 304-315 - [c12]Yakun Sophia Shao, Jason Clemons
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. MICRO 2019: 14-27 - [c11]Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. VLSI Circuits 2019: 300- - [c10]Jie-Fang Zhang
SNAP: A 1.67 - 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS. VLSI Circuits 2019: 306- - [i2]Ameer Haj-Ali, Nesreen K. Ahmed, Theodore L. Willke, Yakun Sophia Shao, Krste Asanovic, Ion Stoica:
NeuroVectorizer: End-to-End Vectorization with Deep Reinforcement Learning. CoRR abs/1909.13639 (2019) - [i1]Hasan Genc, Ameer Haj-Ali, Vighnesh Iyer, Alon Amid, Howard Mao, John Charles Wright, Colin Schmidt, Jerry Zhao, Albert J. Ou, Max Banister, Yakun Sophia Shao, Borivoje Nikolic, Ion Stoica, Krste Asanovic:
Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations of Deep-Learning Architectures. CoRR abs/1911.09925 (2019) - 2018
- [j3]Martha A. Kim, Yakun Sophia Shao:
Hardware Acceleration. IEEE Micro 38(6): 6-7 (2018) - [j2]Rafael Garibotti
Assisting High-Level Synthesis Improve SpMV Benchmark Through Dynamic Dependence Analysis. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1440-1444 (2018) - [c9]Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons
A modular digital VLSI flow for high-productivity SoC design. DAC 2018: 72:1-72:6 - 2017
- [c8]Rafael Garibotti
Using dynamic dependence analysis to improve the quality of high-level synthesis designs. ISCAS 2017: 1-4 - [c7]Brandon Reagen, Yakun Sophia Shao, Sam Likun Xi, Gu-Yeon Wei, David Brooks:
Methods and infrastructure in the era of accelerator-centric architectures. MWSCAS 2017: 902-905 - 2016
- [c6]Yakun Sophia Shao, Sam Likun Xi, Vijayalakshmi Srinivasan, Gu-Yeon Wei, David M. Brooks:
Co-designing accelerators and SoC interfaces using gem5-Aladdin. MICRO 2016: 48:1-48:12 - 2015
- [b1]Yakun Sophia Shao, David M. Brooks:
Research Infrastructures for Hardware Accelerators. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2015, ISBN 978-3-031-00622-7 - [j1]Yakun Sophia Shao, Brandon Reagen, Gu-Yeon Wei, David M. Brooks:
The Aladdin Approach to Accelerator Design and Modeling. IEEE Micro 35(3): 58-70 (2015) - 2014
- [c5]Brandon Reagen, Robert Adolf, Yakun Sophia Shao, Gu-Yeon Wei, David M. Brooks:
MachSuite: Benchmarks for accelerator design and customized architectures. IISWC 2014: 110-119 - [c4]Yakun Sophia Shao, Brandon Reagen, Gu-Yeon Wei, David M. Brooks:
Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures. ISCA 2014: 97-108 - 2013
- [c3]Yakun Sophia Shao, David M. Brooks:
Energy characterization and instruction-level energy model of Intel's Xeon Phi processor. ISLPED 2013: 389-394 - [c2]Brandon Reagen, Yakun Sophia Shao, Gu-Yeon Wei, David M. Brooks:
Quantifying acceleration: Power/performance trade-offs of application kernels in hardware. ISLPED 2013: 395-400 - [c1]Yakun Sophia Shao, David M. Brooks:
ISA-independent workload characterization and its implications for specialized architectures. ISPASS 2013: 245-255
Coauthor Index
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last updated on 2024-11-06 21:32 CET by the dblp team
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