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IEEE Micro, Volume 30, 2010
Volume 30, Number 1, January/February 2010
- Shane M. Greenstein:
The Next Chapter at Google. 4-7 - Trevor N. Mudge:
Guest Editor's Introduction: Top Picks from the Computer Architecture Conferences of 2009. 8-11 - Andrew D. Hilton, Santosh Nagarakatte
, Amir Roth:
iCFP: Tolerating All-Level Cache Misses in In-Order Processors. 12-19 - Nikos Hardavellas
Near-Optimal Cache Block Placement with Reactive Nonuniform Cache Architectures. 29 - John H. Kelm, Daniel R. Johnson, Steven S. Lumetta, Sanjay J. Patel, Matthew I. Frank:
A Task-Centric Memory Model for Scalable Accelerator Architectures. 29-39 - Joseph Devietti, Brandon Lucia, Luis Ceze, Mark Oskin:
DMP: Deterministic Shared-Memory Multiprocessing. 40-49 - Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos:
Making Address-Correlated Prefetching Practical. 50-59 - M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt:
Accelerating Critical Section Execution with Asymmetric Multicore Architectures. 60-70 - Stijn Eyerman, Lieven Eeckhout:
Per-Thread Cycle Accounting. 71-80 - Mark Woh, Sangwon Seo, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner:
AnySP: Anytime Anywhere Anyway Signal Processing. 81-91 - Mohit Tiwari
Gate-Level Information-Flow Tracking for Secure Architectures. 92-100 - Vijay Janapa Reddi, Meeta Sharma Gupta, Glenn H. Holloway, Michael D. Smith, Gu-Yeon Wei, David M. Brooks:
Predicting Voltage Droops Using Recurring Program and Microarchitectural Event Activity. 110 - Constantin Pistol, Wutichai Chongchitmate, Christopher Dwyer, Alvin R. Lebeck:
Architectural Implications of Nanoscale-Integrated Sensing and Computing. 110-120 - Adrian M. Caulfield
Gordon: An Improved Architecture for Data-Intensive Applications. 121-130 - Benjamin C. Lee, Ping Zhou
Phase-Change Technology and the Future of Main Memory. 143 - Richard Mateosian:
Technical Writing. 144-147
Volume 30, Number 2, March/April 2010
- Shane M. Greenstein:
Bleeding-Edge Mass Market Standards. 2-4 - Krste Asanovic, Ralph Wittig:
Guest Editors' Introduction: Hot Chips 21. 5-6 - Ronald N. Kalla, Balaram Sinharoy, William J. Starke, Michael S. Floyd:
Power7: IBM's Next-Generation Server Processor. 7-15 - Pat Conway, Nathan Kalyanasundharam, Gregg Donley, Kevin Lepak, Bill Hughes:
Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor. 16-29 - Takumi Maruyama, Toshio Yoshida, Ryuji Kan, Iwao Yamazaki, Shuji Yamamura, Noriyuki Takahashi, Mikio Hondou, Hiroshi Okano:
Sparc64 VIIIfx: A New-Generation Octocore Processor for Petascale Computing. 30-40 - Bryan Catanzaro, Armando Fox, Kurt Keutzer, David A. Patterson, Bor-Yiing Su, Marc Snir, Kunle Olukotun, Pat Hanrahan, Hassan Chafi:
Ubiquitous Parallel Computing from Berkeley, Illinois, and Stanford. 41-55 - John Nickolls, William J. Dally:
The GPU Computing Era. 56-69 - Tony M. Brewer:
Instruction Set Innovations for the Convey HC-1 Computer. 70-79 - Sassan Tabatabaei, Aaron Partridge:
Silicon MEMS Oscillators for High-Speed Digital Systems. 80-89 - Richard Mateosian:
Designing for Discovery. 90-92
Volume 30, Number 3, May/June 2010
- David H. Albonesi:
Future Directions in Computer Architecture Research. 5 - Shane Greenstein:
Standardization and Coordination. 6-7 - James C. Hoe, Doug Burger, Joel S. Emer, Derek Chiou, Resit Sendag, Joshua J. Yi:
The Future of Architectural Simulation. 8-18 - Arvind, David I. August, Keshav Pingali, Derek Chiou, Resit Sendag, Joshua J. Yi:
Programming Multicores: Do Applications Programmers Need to Write Explicitly Parallel Programs? 19-33 - Elliott Cooper-Balis, Bruce L. Jacob:
Fine-Grained Activation for Power Reduction in DRAM. 34-47 - Hyesook Lim
Tuple Pruning Using Bloom Filters for Packet Classification. 48-59 - Gabriel H. Loh, Yuan Xie:
3D Stacked Microprocessor: Are We There Yet? 60-64
Volume 30, Number 4, July - August 2010
- Shane Greenstein:
Digitization and Value Creation. 4-5 - Luiz André Barroso, Parthasarathy Ranganathan:
Guest Editors' Introduction: Datacenter-Scale Computing. 6-7 - Christoforos E. Kozyrakis, Aman Kansal, Sriram Sankar, Kushagra Vaid:
Server Engineering Insights for Large-Scale Online Services. 8-19 - Trevor N. Mudge, Urs Hölzle:
Challenges and Opportunities for Extremely Energy-Efficient Processors. 20-24 - José E. Moreira, John P. Karidis:
The Case for Full-Throttle Computing: An Alternative Datacenter Design Strategy. 25-28 - Amin Vahdat, Mohammad Al-Fares, Nathan Farrington, Radhika Niranjan Mysore, George Porter, Sivasankar Radhakrishnan:
Scale-Out Networking in the Data Center. 29-41 - Sven-Arne Reinemo
Ethernet for High-Performance Data centers: On the New IEEE Datacenter Bridging Standards. 42-51 - David G. Andersen, Steven Swanson
Rethinking Flash in the Data Center. 52-54 - Peng Wang, Dan Meng, Jizhong Han, Jianfeng Zhan, Bibo Tu, Xiaofeng Shi, Le Wan:
Transformer: A New Paradigm for Building Data-Parallel Programming Models. 55-64 - Gang Ren, Eric Tune, Tipp Moseley, Yixin Shi, Silvius Rus, Robert Hundt:
Google-Wide Profiling: A Continuous Profiling Infrastructure for Data Centers. 65-79 - Benton H. Calhoun, David M. Brooks:
Can Subthreshold and Near-Threshold Circuits Go Mainstream? 80-85 - Richard Mateosian:
Miscellany [Book reviews]. 86-88
Volume 30, Number 5, September - October 2010
- Mateo Valero
Multicore: The View from Europe. 2-4 - Veerle Desmet, Sylvain Girbal
ArchExplorer for Automatic Design Space Exploration. 5-15 - Alex Ramírez, Felipe Cabarcas
The SARC Architecture. 16-29 - Manolis Katevenis, Vassilis Papaefstathiou, Stamatis G. Kavadias, Dionisios N. Pnevmatikatos
Explicit Communication and Synchronization in SARC. 30-41 - Parallel Programming Models for Heterogeneous Multicore Architectures. 42-53
- Stefanos Kaxiras, Georgios Keramidas:
SARC Coherence: Scaling Directory Cache Coherence in Performance and Power. 54-65 - Theo Ungerer, Francisco J. Cazorla
Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability. 66-75 - Yehuda Afek, Ulrich Drepper, Pascal Felber
The Velox Transactional Memory Stack. 76-87 - Koen Bertels, Vlad Mihai Sima
HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms. 88-97 - Shane Greenstein:
Gatekeeping Economics. 102-104
Volume 30, Number 6, November - December 2010
- David H. Albonesi:
Moving Forward. 4-5 - Shane Greenstein:
Building Broadband Ahead of Digital Demand. 6-8 - Ofer Shacham, Omid Azizi, Megan Wachs, Stephen Richardson, Mark Horowitz:
Rethinking Digital Design: Why Design Must Change. 9-24 - Christopher J. Hughes
Performance and Energy Implications of Many-Core Caches for Throughput Computing. 25-35 - Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke:
Putting Faulty Cores to Work. 36-45 - Frederick Ryckbosch, Stijn Polfliet, Lieven Eeckhout:
Fast, Accurate, and Validated Full-System Software Simulation of x86 Hardware. 46-56 - Luk Van Ertvelde, Lieven Eeckhout:
Workload Reduction and Generation Techniques. 57-65 - Roberto Airoldi, Omer Anjum, Fabio Garzia, Alexander M. Wyglinski
Energy-Efficient Fast Fourier Transforms for Cognitive Radio Systems. 66-76 - Richard Mateosian:
Being Geek. 78
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