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Microprocessors and Microsystems, Volume 61
Volume 61, September 2018
- Karyofyllis Patsidis
, Dimitris Konstantinou, Chrysostomos Nicopoulos
A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension. 1-10
- Emad Ebeid
A survey of Open-Source UAV flight controllers and flight simulators. 11-20
- Prasoon Ambalathankandy
Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA. 21-31 - Eleftherios Lygouras
ROLFER: A fully autonomous aerial rescue support system. 32-42
- Robert Hülle, Petr Fiser
ZATPG: SAT-based test patterns generator with zero-aliasing in temporal compaction. 43-57
- Manolis Katevenis, Roberto Ammendola
Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development. 58-71 - Gamil A. Ahmed, Muhammad E. S. Elrabaa
FBNoC: FPGA-based network on chip emulator for full-system architectural simulation of many-core systems. 72-85 - Wasif Afzal
The MegaM@Rt2 ECSEL project: MegaModelling at Runtime - Scalable model-based framework for continuous development and runtime validation of complex systems. 86-95 - Mário P. Véstias
Improving the area of fast parallel decimal multipliers. 96-107
- Macarena C. Martínez-Rodríguez
A comparative analysis of VLSI trusted virtual sensors. 108-116 - Lampros Pyrgas
Compact FPGA architectures for the two-band fast discrete Hartley transform. 117-125 - Maricela Jiménez Rodríguez
A portable embedded system for point-to-point secure signals transmission. 126-134 - Asma Benmessaoud Gabis
Application-aware Multi-Objective Routing based on Genetic Algorithm for 2D Network-on-Chip. 135-153
- José Flich
Exploring manycore architectures for next-generation HPC systems through the MANGO approach. 154-170
- Emanuele Torti
Acceleration of brain cancer detection algorithms during surgery procedures using GPUs. 171-178
- Ching-Han Chen, Leh Luoh, Min-Hao Guo:
A new design and implementation of hardware accelerator for line detection. 179-197
- Luca Pezzarossa, Andreas Toftegaard Kristensen
Using dynamic partial reconfiguration of FPGAs in real-Time systems. 198-206 - Yuanhong Huo, Dake Liu:
High-throughput bit processor for cryptography, error correction, and error detection. 207-216 - Zohre Beiki
Real parallel and constant delay logic circuit design methodology based on the DNA model-of-computation. 217-226 - Anissa Sghaier
High speed and efficient area optimal ate pairing processor implementation over BN and BLS12 curves on FPGA. 227-241
- Seungbum Jo, Markus Lohrey, Damian Ludwig, Simon Meckel, Roman Obermaisser, Simon Plasger:
An architecture for online-diagnosis systems supporting compressed communication. 242-256 - Sundararaman Rajagopalan
ON-Chip peripherals are ON for chaos - an image fused encryption. 257-278
- Ramiro Sámano-Robles
Active flow control using dense wireless sensor and actuator networks. 279-295 - Qaisar Bashir, Muhammad Naeem Shehzad, Muhammad Naeem Awais, Umer Farooq
A scheduling based energy-aware core switching technique to avoid thermal threshold values in multi-core processing systems. 296-305 - Laurence Crestani Tasca, Edison Pignaton de Freitas
Enhanced architecture for programmable logic controllers targeting performance improvements. 306-315
- Florian Neugebauer, Ilia Polian, John P. Hayes
S-box-based random number generation for stochastic computing. 316-326
- Saeid Zoka, Mohammad Gholami
A novel rising Edge Triggered Resettable D flip-flop using five input majority gate. 327-335 - Li Li, Fenghua Li, Kui Geng, Guozhen Shi:
Design of Multi Cipher Processing Architecture for Random Cross Access. 336-343
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