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10th PATMOS 2000: Göttingen, Germany
- Dimitrios Soudris, Peter Pirsch, Erich Barke:
Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings. Lecture Notes in Computer Science 1918, Springer 2000, ISBN 3-540-41068-6
Opening
- Rene van Leuken, Reinder Nouta, Alexander de Graaf:
Constraints, Hurdles, and Opportunities for a Successful European Take-Up Action. 1-2
RTL Power Modeling
- Manuela Anton, Mauro Chinosi, Daniele Sirtori, Roberto Zafalon:
Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques. 3-13 - Alessandro Bogliolo, Enrico Macii, Virgil Mihailovici, Massimo Poncino:
Power Models for Semi-autonomous RTL Macros. 14-23 - Gerd Jochens, Lars Kruse, Eike Schmidt, Ansgar Stammermann, Wolfgang Nebel:
Power Macro-Modelling for Firm-Macro. 24-35 - Crina Anton, Pierluigi Civera, Ionel Colonescu, Enrico Macii, Massimo Poncino, Alessandro Bogliolo:
RTL Estimation of Steering Logic Power. 36-46
Power Estimation and Optimization
- Nikolaos D. Zervas, S. Theoharis, Athanasios Kakarountas, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis:
Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers. 47-55 - Achim Freimann:
Framework for High-Level Power Estimation of Signal Processing Architectures. 56-65 - Claudia Kretzschmar, Robert Siegmund, Dietmar Müller:
Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses. 66-75 - George Theodoridis, S. Theoharis, Nikolaos D. Zervas, Constantinos E. Goutis:
Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions. 76-87
System-Level Design
- Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam:
A Holistic Approach to System Level Energy Optimization. 88-107 - Marcello Lajolo, Luciano Lavagno, Matteo Sonza Reorda
, Massimo Violante:
Early Power Estimation for System-on-Chip Designs. 108-117 - Reiner W. Hartenstein, Thomas Hoffmann, Ulrich Nageldinger:
Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures. 118-128
Transistor-Level Modeling
- Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne:
Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design. 129-138 - Henrik Eriksson, Per Larsson-Edefors:
Impact of Voltage Scaling on Glitch Power Consumption. 139-148 - Jorge Juan-Chico, Manuel J. Bellido
Degradation Delay Model Extension to CMOS Gates. 149-158 - Mustapha Rezzoug, Philippe Maurine, Daniel Auvergne:
Second Generation Delay Model for Submicron CMOS Process. 159-167
Asynchronous Circuit Design
- Nikolai Starodoubtsev, Alexandre V. Bystrov
Semi-modular Latch Chains for Asynchronous Circuit Design. 168-177 - Francesco Pessolano, Joep L. W. Kessels:
Asynchronous First-in First-out Queues. 178-186 - Athanasios Kakarountas, Kyriakos Papadomanolakis, Vasileios Kokkinos, Constantinos E. Goutis:
Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance. 187-194 - Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo:
VLSI Implementation of a Low-Power High-Speed Self-Timed Adder. 195-204
Power Efficient Technologies
- Holger Sedlak:
Low Power Design Techniques for Contactless Chipcards. 205-206 - Joohee Kim, Marios C. Papaefthymiou:
Dynamic Memory Design for Low Data-Retention Power. 207-216 - Claude Arm, Jean-Marc Masgonty, Christian Piguet:
Double-Latch Clocking Scheme for Low-Power I.P. Cores. 217-224
Design of Multimedia Processing Applications
- Santanu Dutta:
Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip. 225-232 - Kristof Denolf, Peter Vos, Jan Bormans, Ivo Bolsens:
Cost-Efficient C-Level Design of an MPEG-4 Video Decoder. 233-242 - Dimitrios Soudris, Nikolaos D. Zervas, Antonios Argyriou, Minas Dasygenis, Konstantinos Tatas
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications. 243-254
Adiabatic Design and Arithmetic Modules
- Alexis De Vos, Bart Desoete, Artur Adamski, Piotr Pietrzak, Maciej Sibínski
Design of Reversible Logic Circuits by Means of Control Gates. 255-264 - Massimo Alioto, Gaetano Palumbo:
Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates. 265-275 - Christoph Saas, Andreas Schlaffer, Josef A. Nossek:
An Adiabatic Multiplier. 276-284 - Vassilis Paliouras
Logarithmic Number System for Low-Power Arithmetic. 285-294
Analog-Digital Circuits Modeling
- Raúl Jiménez, Antonio J. Acosta, Eduardo J. Peralías, Adoración Rueda:
An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits. 295-305 - Andreas Herrmann, Erich Barke, Mathias Silvant, Jürgen Schlöffel:
PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits. 306-315 - Antonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. 316-326 - Tim Wichmann, Manfred Thole:
Computer Aided Generation of Analytic Models for Nonlinear Function Blocks. 327-335
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