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ISPASS 2000: Austin, Texas, USA
- 2000 IEEE International Symposium on Performance Analysis of Systems and Software, April 24-35, 2000, Austin, Texas, USA, Proceedings. IEEE Computer Society 2000, ISBN 0-7803-6418-X
- Lieven Eeckhout, Koen De Bosschere, Henk Neefs:
Performance analysis through synthetic trace generation. 1-6 - Nicola Zingirian, Massimo Maresca:
Extracting fine-grain profiles of in-order executions of instruction level parallel programs. 7-12 - John Kalamatianos, David R. Kaeli:
Accurate simulation and evaluation of code reordering. 13-20 - Hsien-Hsin S. Lee
, Youfeng Wu, Gary S. Tyson:
Quantifying instruction-level parallelism limits on an EPIC architecture. 21-27 - Luís Fernando Friedrich, Rafael Luiz Cancian
Performance evaluation of real-time scheduling on a multicomputer architecture. 28-33 - Rod Fatoohi, Vandana Gunwani, Qi Wang, Charlton Zheng:
Performance evaluation of middleware bridging technologies. 34-39 - David A. Cargill, Mohammad Radaideh:
A practitioner report on the evaluation of the performance of the C, C++ and Java compilers on the OS/390 platform. 40-45 - Maryela Weihrauch:
DB2 for OS/390 V5 vs. V6 outer join performance. 46-51 - Moez Yeddes, Hassane Alla:
Checking order-insensitivity using ternary simulation in synchronous programs. 52-57 - Witawas Srisa-an, J. Morris Chang, Chia-Tien Dan Lo:
Do generational schemes improve the garbage collection efficiency? 58-63 - Chia-Tien Dan Lo, Witawas Srisa-an
A quantitative simulator for dynamic memory managers. 64-69 - Hong Liu, Hongdu Fang:
Real-time image on QoS Web. 70-75 - Ravi Bhargava, Lizy K. John:
Issues in the design of store buffers in dynamically scheduled processors. 76-87 - Jess Rupley II, David C. Holloway:
Performance tradeoffs in sequencer design on a new G4 PowerPCTM microprocessor. 88-94 - Murali Annavaram
Instruction overhead and data locality effects in superscalar processors. 95-100 - Luis M. Ramos, Pablo E. Ibáñez
Modeling load address behaviour through recurrences. 101-108 - Renato Recio, W. Todd Boyd:
Methodology to optimize the cost/performance of disk subsystems. 109-115 - Andrea Barisone, Francesco Bellotti, Riccardo Berta
Invocation profile characterization of Java applications. 116-122 - Eric Kronstadt:
Some observations based on simple models of MP scaling. 123-128 - Shikharesh Majumdar:
Performance scalability in multiprocessor systems with resource contention. 129-138 - Nerina Bermudo, Xavier Vera, Antonio González
An efficient solver for Cache Miss Equations. 139-145 - Vivek Sarkar, Nimrod Megiddo:
An analytical model for loop tiling and its solution. 146-153 - Tilman Wolf, Mark A. Franklin:
CommBench-a telecommunications benchmark for network processors. 154-162 - Karel Driesen, Josee Colette, Feng Ji, Mathias Jourdain, Mazen Fahmi, Abeer Ghuneim, Edil Hersi, Joyce Kahwa, Hala Razi Khan, Cathy Kwan, Abbas Mahyari, Jerome Miecknikowski, Mourad Oulmane, Michele Perucic, Azir Pirbay, Luiza Solomon, Jean Jac Taoko, Lip Hooi Tan, Feng Qian, Honghao Zhang, Lingyan Zhang, Su Zhang, Will Renner:
Simplified workload characterization using unified prediction. 163-171 - María Engracia Gómez
A new approach in the analysis and modeling of disk access patterns. 172-177 - Jerzy Jagiello, N. Tay, B. Biddington, R. Dacray:
Mobile functionality in a pervasive world. 178-183 - Junehwa Song, Eric Levy-Abegnoli, Arun Iyengar, Daniel M. Dias:
Design alternatives for scalable Web server accelerators. 184-192 - Avinoam N. Eden, Brian W. Joh, Trevor N. Mudge:
Web latency reduction via client-side prefetching. 193-200 - Krishna Kant, C. R. M. Sundaram:
A server performance model for static Web workloads. 201-206
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