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ICCAD 1988: Santa Clara, California, USA
- 1988 IEEE International Conference on Computer-Aided Design, ICCAD 1988, Santa Clara, CA, USA, November 7-10, 1988. Digest of Technical Papers. IEEE Computer Society 1988, ISBN 0-8186-0869-2
- Masahiro Fujita, Hisanori Fujisawa, Nobuaki Kawato:
Evaluation and improvement of Boolean comparison method based on binary decision diagrams. 2-5 - Sharad Malik
, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Logic verification using binary decision diagrams in a logic synthesis environment. 6-9 - Hyunwoo Cho, Gary D. Hachtel, M. Nash, L. Setiono:
BEATNP: a tool for partitioning Boolean networks. 10-13 - K. K. Low, Stephen W. Director:
An efficient macromodeling approach for statistical IC process design. 16-19 - Tat-Kwan Yu, Sung-Mo Kang, Ibrahim N. Hajj, Timothy N. Trick:
iEDISON: an interactive statistical design tool for MOS VLSI circuits. 20-23 - Sung-Mo Kang, Yusuf Leblebici:
An efficient method for circuit sensitivity calculation using piecewise linear waveform models. 24-27 - Pin-San Tzeng, Carlo H. Séquin:
Codar: a congestion-directed general area router. 30-33 - Pierre-François Dubois, Alain Puissochet, Anne-Marie Tagant:
Carioca-A 'smart' and flexible switch-box router. 34-37 - Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai:
A detailed router based on simulated evolution. 38-41 - Baher Haroun, Mohamed I. Elmasry:
Automatic synthesis of a multi-bus architecture for DSP. 44-47 - Rajiv Jain, Mitch J. Mlinar, Alice C. Parker:
Area-time model for synthesis of non-pipelined designs. 48-51 - Ki Soo Hwang, Albert E. Casavant, Martin Dragomirecky, Manuel A. d'Abreu:
Constrained conditional resource sharing in pipeline synthesis. 52-55 - Gaetano Borriello:
Combining event and data-flow graphs in behavioral synthesis. 56-59 - Russell Kao, Bob Alverson, Mark Horowitz, Don Stark:
Bisim: a simulator for custom ECL circuits. 62-65 - Romy L. Bauer, Jiayuan Fang, Antony P.-C. Ng, Robert K. Brayton:
XPSim: a MOS VLSI simulator. 66-69 - David Overhauser, Ibrahim N. Hajj:
A tabular macromodeling approach to fast timing simulation including parasitics. 70-73 - Takayasu Sakurai:
CMOS inverter delay and other formulas using alpha -power law MOS model. 74-77 - Jingsheng Cong, C. L. Liu:
Over-the-cell channel routing. 80-83 - H. Zhu, Robert H. Fujii:
Net characterization based channel router: FT router. 84-87 - Ronald I. Greenberg, Alexander T. Ishii, Alberto L. Sangiovanni-Vincentelli:
MulCh: a multi-layer channel router using one, two, and three layer partitions. 88-91 - Gary D. Hachtel, Reily M. Jacoby, P. Moceyunas, Christopher R. Morrison:
Performance enhancements in BOLD using 'implications'. 94-97 - Robert K. Brayton, Ellen M. Sentovich, Fabio Somenzi:
Don't cares and global flow analysis of Boolean networks. 98-101 - C. Leonard Berman, Louise Trevillyan:
Improved logic optimization using global flow analysis. 102-105 - Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
A modified approach to two-level logic minimization. 106-109 - Kartikeya Mayaram, Donald O. Pederson:
CODECS: a fixed mixed-level device and circuit simulator. 112-115 - Akio Yajima, Hirofumi Jonishi, Akihisa Maruyama:
A grid generation system for process and device simulation. 116-119 - Abhijit Chatterjee, Charles F. Machala III, Ping Yang:
A submicron MOSFET model for simulation of analog circuits. 120-123 - Phillip E. Allen, Kwang S. Yoon:
A table look-up MOSFET model for analog applications. 124-127 - Shuo Huang, Omar Wing:
Gate matrix partitioning. 130-133 - Lukas P. P. P. van Genneken, Jos T. J. van Eijndhoven, Jos A. H. C. M. Brouwers:
Doubly folded transistor matrix layout. 134-137 - C. Y. Roger Chen, Cliff Yungchin Hou:
A new algorithm for CMOS gate matrix layout. 138-141 - Paul Kollaritsch, Steve Lusky, Sharat Prasad, Neil Potter:
CLAY: a malleable-cell multi-cell transistor matrix approach for CMOS LAYout synthesis. 142-145 - Srinivas Devadas, A. Richard Newton:
Decomposition and factorization of sequential finite state machines. 148-151 - Devadas Varma, Eliezer A. Trachtenberg:
A fast algorithm for the optimal state assignment of large finite state machines. 152-155 - José L. Huertas, José M. Quintana:
A new method for the efficient state-assignment of PLA-based sequential machines. 156-159 - Prem R. Menon, Ytzhak H. Levendel, Miron Abramovici:
Critical path tracing in sequential circuits. 162-165 - Wuudiann Ke, Sharad C. Seth, Bhargab B. Bhattacharya:
A fast fault simulation algorithm for combinational circuits. 166-169 - Fadi Maamari, Janusz Rajski:
A fault simulation method based on stem regions. 170-173 - Jinepheng Cong, Bryan Preas:
A new algorithm for standard cell global routing. 176-179 - Kai-Win Lee, Carl Sechen:
A new global router for row-based layout. 180-183 - Mohankumar Guruswamy, Martin D. F. Wong
Channel routing order for building-block layout with rectilinear modules. 184-187 - Pradip Bose:
Parallel logic/fault simulation of VLSI array logic. 190-193 - Eli Chiprout, Janusz Rajski, Markus Robinson:
Parallel PLA fault simulation based on Boolean vector operations. 194-197 - Füsun Özgüner, Raja Daoud:
Vectorized fault simulation on the Cray X-MP supercomputer. 198-201 - Farid N. Najm, Richard Burch, Ping Yang, Ibrahim N. Hajj:
CREST-a current estimator for CMOS circuits. 204-207 - An-Chang Deng, Yan-Chyuan Shiau, K.-H. Loh:
Time domain current waveform simulation of CMOS circuits. 208-211 - S. Chowdhury, Javed Sabir Barkatullah:
Current estimation in MOS IC logic circuits. 212-215 - Fred W. Obermeier, Randy H. Katz:
Combining circuit level changes with electrical optimization. 218-221 - Chun-Ping George Chi:
A method for net representation with polygon decomposition. 222-225 - F. Gourdy, Alain Greiner, M. Guillemet, Roland Marbot, J. Murzin:
NOISY: an electrical noise checker for ULSI. 226-229 - Robert C. Aitken, Vinod K. Agarwal:
Aliasing probability of non-exhaustive randomized syndrome tests. 232-235 - Ramaswami Dandapani, Ravi K. Gulati, Deepak K. Goel:
Built-in self-test for large embedded CMOS folded PLAs. 236-239 - Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha:
On the design of robust multiple fault testable CMOS combinational logic circuits. 240-243 - Takuji Ogihara, Shuichi Saruyama, Shinichi Murai:
Test generation for sequential circuits using individual initial value propagation. 242-247 - Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Jacob A. Abraham, Joseph T. Rahmeh:
CHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits. 246-249 - Michel Heydemann, Daniel Dure:
The logic automation approach to accurate and efficient gate and functional level simulation. 250-253 - Donald Thelen, John MacDonald:
Simulating mixed analog-digital circuits on a digital simulator. 254-257 - Rakesh Chadha, Chin-Fu Chen:
M3-a multilevel mixed-mode mixed D/A simulator. 258-261 - S. P. Smith, J. Kuban:
Modeling and enhancing virtual memory performance in logic simulation. 264-267 - Ram Raghavan, John P. Hayes, William R. Martin:
Logic simulation on vector processors. 268-271 - Roger D. Chamberlain, Mark A. Franklin:
Discrete-event simulation on hypercube architectures. 272-275 - Rod D. W. Widdowson, Kenny Ferguson:
Parallel polygon operations using loosely coupled workstations. 276-279 - Kanwar Jit Singh, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Timing optimization of combinational logic. 282-285 - Michael R. Lightner, Wayne H. Wolf:
Experiments in logic optimization. 286-289 - Srinivas Devadas, Albert R. Wang, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
Boolean decomposition in multi-level logic optimization. 290-293 - Daniel Brand:
Hill climbing with reduced search space (logic optimization). 294-297 - David C. Yeh, Vasant B. Rao:
Partitioning issues in circuit simulation on multiprocessors. 300-303 - Mi-Chang Chang, Ibrahim N. Hajj:
iPRIDE: a parallel integrated circuit simulator using direct method. 304-307 - Andrew Lumsdaine, Jacob White, Donald M. Webber, Alberto L. Sangiovanni-Vincentelli:
A band relaxation algorithm for reliable and parallelizable circuit simulation. 308-311 - Jack V. Briner Jr., John L. Ellis, Gershon Kedem:
Taking advantage of optimal on-chip parallelism for parallel discrete-event simulation. 312-315 - Masayuki Sato, Noriaki Ohba, Hiromi Watanabe, Shozo Saito:
Stick diagram extraction program SKELETON. 318-321 - Carl Ebeling:
GeminiII: a second generation layout validation program. 322-325 - Krishna P. Belkhale, Prithviraj Banerjee:
PACE: a parallel VLSI extractor on the Intel hypercube multiprocessor. 326-329 - J. C. Jeong, S. Y. Shin, C. D. Lee, Y. U. Yu:
An efficient sequential range query model for minimum width/space verification (circuit analysis). 330-333 - Jay B. Brockman, Stephen W. Director:
Predictive subset testing for IC performance. 336-339 - Wojciech Maly, Phil Nigh:
Built-in current testing-feasibility study. 340-343 - Wojciech Maly, Pranab K. Nag, Phil Nigh:
Testing oriented analysis of CMOS ICs with opens. 344-347 - Prathima Agrawal, Scott H. Robinson, Thomas G. Szymanski:
Automatic modeling of switch-level networks using partial orders. 350-353 - Randal E. Bryant:
Data parallel switch-level simulation. 354-357 - Denis Martin, Nicholas C. Rumin:
Delay computation in switch-level models of non-treelike MOS circuits. 358-361 - André Stauffer, Ravi Nair:
Optimal CMOS cell transistor placement: a relaxation approach. 364-367 - C. Y. Roger Chen, Cliff Yungchin Hou:
A new layout optimization methodology for CMOS complex gates. 368-371 - H. Y. Chen, Sung-Mo Kang:
iCOACH: a circuit optimization aid for CMOS high-performance circuits. 372-375 - Ravi K. Gulati, Deepak K. Goel:
An efficient compaction algorithm for test vectors of microprocessors and microcontrollers. 378-381 - Rabindra K. Roy, Thomas M. Niermann, Janak H. Patel, Jacob A. Abraham, Resve A. Saleh:
Compaction of ATPG-generated test sequences for sequential circuits. 382-385 - Tom Kronmiller:
Efficient handling of large wiring data in TANGATE. 388-391 - Melvin A. Breuer, Wesley H. Cheng, Rajiv Gupta, Ido Hardonag, Ellis Horowitz, S. Y. Lin:
Cbase 1.0: a CAD database for VLSI circuits using object oriented technology. 392-395 - William D. Smith, Jeffrey R. Jasica, Michael J. Hartman, Manuel A. d'Abreu:
Flexible module generation in the FACE design environment. 396-399 - James P. Cohoon, Dana S. Richards, Jeffrey S. Salowe:
A linear-time Steiner tree routing algorithm for terminals on the boundary of a rectangle. 402-405 - Shinichiro Haruyama, Martin D. F. Wong
Topological channel routing. 406-409 - Xiao-Ming Xiong:
A new algorithm for topological routing and via minimization. 410-413 - Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal:
Automatic test generation using neural networks. 416-419 - Gerd Krüger:
A tool for hierarchical test generation. 420-423 - Abhijit Chatterjee, Jacob A. Abraham:
NCUBE: an automatic test generation program for iterative logic arrays. 428-431 - Bill Nye:
First order nonlinear device bypass in circuit simulation. 434-437 - Paul F. Cox, Richard Burch, Ping Yang:
A dormant subcircuit model for maximizing iteration latency. 438-441 - Peter Saviz, Omar Wing:
PYRAMID-a hierarchical waveform relaxation-based circuit simulation program. 442-445 - Kenneth S. Kundert, Jacob White, Alberto L. Sangiovanni-Vincentelli:
An envelope-following method for the efficient transient simulation of switching power and filter circuits. 446-449 - James P. Cohoon, Shailesh U. Hegde, Worthy N. Martin, Dana Richards:
Floorplan design using distributed genetic algorithms. 452-455 - Mark Hirsch, Daniel P. Siewiorek:
Automatically extracting structure from a logical design. 456-459 - Bernhard Eschermann, Wayne Wei-Ming Dai, Ernest S. Kuh, Massoud Pedram:
Hierarchical placement for macrocells: a 'meet in the middle' approach. 460-463 - Reinaldo A. Bergamaschi:
Automatic synthesis and technology mapping of combinational logic. 466-469 - Michel R. C. M. Berkelaar, Jochen A. G. Jess:
Technology mapping for standard-cell generators. 470-473 - Kuang-Chien Chen, Saburo Muroga:
Input assignment algorithm for decoded-PLAs with multi-input decoders. 474-477 - Alexander Saldanha, Randy H. Katz:
PLA optimization using output encoding. 478-481 - Jyuo-Min Shyu, Alberto L. Sangiovanni-Vincentelli:
ECSTASY: a new environment for IC design optimization. 484-487 - Steven J. Seda, Marc G. R. Degrauwe, Wolfgang Fichtner:
A symbolic analysis tool for analog circuit design automation. 488-491 - Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley:
Analog circuit synthesis for performance in OASYS. 492-495 - John G. Kenney, L. Richard Carley:
CLANS: a high-level synthesis tool for high resolution data converters. 496-499 - Carl Sechen, Dahe Chen:
An improved objective function for mincut circuit partitioning. 502-505 - Jürgen M. Kleinhans, Georg Sigl, Frank M. Johannes:
GORDIAN: a new global optimization/rectangle dissection method for cell placement. 506-509 - Jimmy Lam, Jean-Marc Delosme:
Simulated annealing: a fast heuristic for some generic layout problems. 510-513 - Jonathan Rose, Wolfgang Klebsch, Jürgen Wolf:
Temperature measurement of simulated annealing placements. 514-517 - Nany Hasan, Jason Cong, C. L. Liu:
A new formulation of yield enhancement problems for reconfigurable chips. 520-523 - Ming-Feng Chang, W. Kent Fuchs, Janak H. Patel:
Diagnosis and repair of memory with coupling faults. 524-527 - Wanhao Li, Scott Legendre, Kevin Gardiner:
Two-layer quad trees: a data structure for high-speed interactive layout tools. 530-533 - Nils Hedenstierna, Kjell O. Jeppson:
The use of inverse layout trees for hierarchical design verification. 534-537 - Michael Quayle, Jon A. Solworth:
Expanded rectangles: a new VLSI data structure. 538-541 - David J. Garrod, Rob A. Rutenbar, L. Richard Carley:
Automatic layout of custom analog cells in ANAGRAM. 544-547 - Han Young Koh, Carlo H. Séquin, Paul R. Gray:
Automatic layout generation for CMOS operational amplifiers. 548-551
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