default search action
33rd FPL 2023: Gothenburg, Sweden
- Nele Mentens, Leonel Sousa, Pedro Trancoso, Nikela Papadopoulou, Ioannis Sourdis:
33rd International Conference on Field-Programmable Logic and Applications, FPL 2023, Gothenburg, Sweden, September 4-8, 2023. IEEE 2023, ISBN 979-8-3503-4151-5 - Ioannis Sourdis, Nele Mentens, Leonel Sousa, Pedro Trancoso:
Preface. xiii - Robert Szafarczyk, Syed Waqar Nabi, Wim Vanderbauwhede:
Compiler Discovered Dynamic Scheduling of Irregular Code in High-Level Synthesis. 1-9 - Gabriel Rodriguez-Canal, Nick Brown
, Tim Dykes, Jessica R. Jones, Utz-Uwe Haus:
Fortran High-Level Synthesis: Reducing the Barriers to Accelerating HPC Codes on FPGAs. 10-18 - Louis Ledoux
An Open-Source Framework for Efficient Numerically-Tailored Computations. 19-26 - Yuntao Han, Qiang Liu:
HPTA: A High Performance Transformer Accelerator Based on FPGA. 27-33 - Hanning Chen, Ali Zakeri, Fei Wen, Hamza Errahmouni Barkam, Mohsen Imani:
HyperGRAF: Hyperdimensional Graph-Based Reasoning Acceleration on FPGA. 34-41 - Shiqing Li, Shien Zhu
An Efficient Sparse LSTM Accelerator on Embedded FPGAs with Bandwidth-Oriented Pruning. 42-48 - Tiandong Zhao, Siyuan Miao, Shaoqiang Lu, Jialin Cao, Jun Qiu, Xiao Shi, Kun Wang, Lei He:
Token Packing for Transformers with Variable-Length Inputs. 49-56 - Kimia Talaei Khoozani, Arash Ahmadian Dehkordi, Vaughn Betz:
Titan 2.0: Enabling Open-Source CAD Evaluation with a Modern Architecture Capture. 57-64 - Tan Nguyen, Zachary Blair, Stephen Neuendorffer, John Wawrzynek:
SPADES: A Productive Design Flow for Versal Programmable Logic. 65-71 - Ruichen Chen, Shengyao Lu, Mohamed A. Elgammal, Peter Chun, Vaughn Betz, Di Niu:
VPR-Gym: A Platform for Exploring AI Techniques in FPGA Placement Optimization. 72-78 - Nicolai Müller, Sergej Meschkov, Dennis R. E. Gnad, Mehdi B. Tahoori, Amir Moradi:
Automated Masking of FPGA-Mapped Designs. 79-85 - Petros Toupas
fpgaHART: A Toolflow for Throughput-Oriented Acceleration of 3D CNNs for HAR onto FPGAs. 86-92 - Haishuang Fan
Co-ViSu: a Video Super-Resolution Accelerator Exploiting Codec Information Reuse. 93-100 - Luyang Yu, Yizhen Lu, Meghna Mandava, Edward Richter, Vikram Sharma Mailthody, Seungwon Min, Wen-Mei W. Hwu, Deming Chen:
FSSD: FPGA-Based Emulator for SSDs. 101-108 - M. D. Arafat Kabir, Ehsan Kabir, Joshua Hollis, Eli Levy-Mackay, Atiyehsadat Panahi, Jason D. Bakos, Miaoqing Huang, David Andrews:
FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ? 109-115 - Pengyu Liu
Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture. 116-122 - Shaden M. Alismail, Dirk Koch:
Efficient Resource Scheduling for Runtime Reconfigurable Systems on FPGAs. 123-129 - Amin Mohaghegh, Vaughn Betz:
Tear Down The Wall: Unified and Efficient Intra-and Inter-Cluster Routing for FPGAs. 130-136 - Rémi Garcia
Multiple Constant Multiplication: From Target Constants to Optimized Pipelined Adder Graphs. 137-143 - Lukas Stasytis, Zsolt István:
Optimization Techniques for Hestenes-Jacobi SVD on FPGAs. 144-150 - José Oliver, Carlos Álvarez
Accelerating SpMV on FPGAs Through Block-Row Compress: A Task-Based Approach. 151-158 - Changjun Song, Yongming Tang, Jiyuan Liu
MSDF-SGD: Most-Significant Digit-First Stochastic Gradient Descent for Arbitrary-Precision Training. 159-165 - Joshua Lant, Emmanouil Skordalakis, Kyriakos Paraskevas
DiAD - Distributed Acceleration for Datacenter FPGAs. 166-173 - Yang Yang, Weihang Long, Rajgopal Kannan, Viktor K. Prasanna:
FPGA Acceleration of Rotation in Homomorphic Encryption Using Dynamic Data Layout. 174-181 - Ce Guo, Diego Cupello, Wayne Luk, Joshua M. Levine, Alexander Warren, Peter Brookes:
FPGA-Accelerated Causal Discovery with Conditional Independence Test Prioritization. 182-188 - Tobias Hahn
SPEAR-JSON: Selective Parsing of JSON to Enable Accelerated Stream Processing on FPGAs. 189-196 - Baoze Zhao, Wenjin Huang, Yihua Huang:
A Novel Hardware Accelerator of NeRF Based on Xilinx UltraScale and UltraScale+ FPGA. 197-203 - Zhewen Yu, Christos-Savvas Bouganis:
Mixed-TD: Efficient Neural Network Accelerator with Layer-Specific Tensor Decomposition. 204-211 - Stefan Abi-Karam
GNNBuilder: An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization. 212-218 - Paul Chen, Pavan Manjunath, Sasindu Wijeratne, Bingyi Zhang, Viktor K. Prasanna:
Exploiting On-Chip Heterogeneity of Versal Architecture for GNN Inference Acceleration. 219-227 - Ruiqi Chen
Graph-OPU: A Highly Integrated FPGA-Based Overlay Processor for Graph Neural Networks. 228-234 - Shashwat Khandelwal, Shanker Shreejith
Exploring Highly Quantised Neural Networks for Intrusion Detection in Automotive CAN. 235-241 - Zizhang Luo, Liqiang Lu, Yicheng Jin, Liancheng Jia, Yun Liang:
Calabash: Accelerating Attention Using a Systolic Array Chain on FPGAs. 242-247 - Zhiqiang Que, Shuo Liu, Markus Rognlien, Ce Guo, José Gabriel F. Coutinho, Wayne Luk:
MetaML: Automating Customizable Cross-Stage Design-Flow for Deep Learning Acceleration. 248-252 - Mohammadmahdi Mazraeli, Yu Gao, Paul Chow:
Partitioning Large-Scale, Multi-FPGA Applications for the Data Center. 253-258 - Vincent Meyers, Michael Hefenbrock, Dennis Gnad, Mehdi Baradaran Tahoori:
Remote Identification of Neural Network FPGA Accelerators by Power Fingerprints. 259-264 - Andrew Boutros, Stephen More, Vaughn Betz:
A Whole New World: How to Architect Beyond-FPGA Reconfigurable Acceleration Devices? 265-270 - Huimin Li, Phillip Rieger, Shaza Zeitouni, Stjepan Picek, Ahmad-Reza Sadeghi:
FLAIRS: FPGA-Accelerated Inference-Resistant & Secure Federated Learning. 271-276 - Martin Langhammer, George A. Constantinides:
eGPU: A 750 MHz Class Soft GPGPU for FPGA. 277-282 - Yueyin Bai, Hao Zhou, Keqing Zhao, Manting Zhang, Jianli Chen, Jun Yu, Kun Wang:
LTrans-OPU: A Low-Latency FPGA-Based Overlay Processor for Transformer Networks. 283-287 - Alexander Montgomerie-Corcoran, Zhewen Yu, Jianyi Cheng, Christos-Savvas Bouganis:
PASS: Exploiting Post-Activation Sparsity in Streaming Architectures for CNN Acceleration. 288-293 - Shi-Yu Huang, Yun-Chen Yang, Yu-Ru Su, Bo-Cheng Lai, Javier M. Duarte
Low Latency Edge Classification GNN for Particle Trajectory Tracking on FPGAs. 294-298 - Vaibhav Kashera, Siddhant Jain, Abhishek Banerjee, Suresh Purini:
Building Low-Latency Order Books with Hybrid Binary-Linear Search Data Structures on FPGAs. 299-304 - Guanglei Zhou, Mirjana Stojilovic, Jason Helge Anderson:
GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors. 305-310 - Hayden Cook, Zephram Tripp, Brad L. Hutchings, Jeffrey Goeders:
Improving the Reliability of FPGA CRO PUFs. 311-316 - Ruiqi Chen
FPGA Accelerating Multi-Source Transfer Learning with GAT for Bioactivities of Ligands Targeting Orphan G Protein-Coupled Receptors. 317-321 - Yang Liu
DIF-LUT: A Simple Yet Scalable Approximation for Non-Linear Activation Function on FPGA. 322-326 - Ehsan Kabir, Daniel Coble, Joud N. Satme, Austin R. J. Downey
Accelerating LSTM-Based High-Rate Dynamic System Models. 327-332 - Jonas Krautter, Paul R. Genssler, Gloria Sepanta, Hussam Amrouch, Mehdi B. Tahoori:
Stress-Resiliency of AI Implementations on FPGAs. 333-338 - Christoph Niemann, Michael Rethfeldt, Dirk Timmermann:
A Novel Strategy for Flexible Placement and Routing of AVS Sensors on FPGAs. 339-344 - Ziyi Yang
Exploring FPGA Acceleration for Distributed Serverless Computing. 345-346 - Philipp Kreowsky, Justin Knapheide, Benno Stabernack:
Challenges Using FPGA Clusters for Distributed CNN Training. 347-348 - Rubén Macias, Sergio Bernabé, Carlos González:
Accelerating the ATDCA Algorithm for Endmember Extraction from Hyperspectral Imagery with Intel oneAPI for FPGAs. 349-350 - Zhenya Zang, Uwe Dolinsky, Pietro Ghiglio, Stefano Cherubin
Building a Reusable and Extensible Automatic Compiler Infrastructure for Reconfigurable Devices. 351-352 - Xiaorang Guo, Martin Schulz
A Scalable and Cross-Technology Quantum Control Processor. 353-354 - Xuqi Zhu, Cong Gao, Sangeet Saha, Xiaojun Zhai, Klaus D. McDonald-Maier:
Bayesian Optimization for Efficient Heterogeneous MPSoC Based DNN Accelerator Runtime Tuning. 355-356 - Veronia Iskandar, Mohamed A. Abd El Ghany, Diana Goehringer
Performance Estimation and Prototyping of Reconfigurable Near-Memory Computing Systems. 357-358 - Felix Jentzsch:
Hardware-Aware AutoML for Exploration of Custom FPGA Accelerators for RadioML. 359-360 - Hans Jakob Damsgaard
Towards Coarse-Grained Reconfigurable Approximate Computing with CGRAgen. 361-362 - Justin Knapheide, Philipp Kreowsky, Benno Stabernack:
Demonstrating NADA: A Workflow for Distributed CNN Training on FPGA Clusters. 363 - Michael Offel, Andreas Ley, Sven Hager:
HashCache: High-Performance State Tracking for Resilient FPGA-Based Packet Processing. 364 - Myrtle Shah, Jakob Ternes, Dirk Koch:
FABulous Demo: Open Source FPGA on Sky130. 365 - Yunyi Zhao, Yunjia Xia, Rui C. V. Loureiro, Hubin Zhao, Uwe Dolinsky, Shufan Yang
FPL Demo: A Learning-Based Motion Artefact Detector for Heterogeneous Platforms. 366
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-22 19:50 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: