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15th ATS 2006: Fukuoka, Japan
- 15th Asian Test Symposium, ATS 2006, Fukuoka, Japan, November 20-23, 2006. IEEE 2006, ISBN 0-7695-2628-4
- Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty
, Serge Pravossoudovitch, Christian Landrault:
Power-Aware Test Data Compression for Embedded IP Cores. 5-10 - Jia Li, Yu Hu, Xiaowei Li:
A Scan Chain Adjustment Technology for Test Power Reduction. 11-16 - Youbean Kim, Dongsup Song, Kicheol Kim, Incheol Kim, Sungho Kang:
TOSCA: Total Scan Power Reduction Architecture based on Pseudo-Random Built-in Self Test Structure. 17-24 - Li-Ming Denq, Tzu-chiang Wang, Cheng-Wen Wu
An Enhanced SRAM BISR Design with Reduced Timing Penalty. 25-30 - Alfredo Benso
Memory Fault Simulator for Static-Linked Faults. 31-36 - Baosheng Wang, Qiang Xu
Test/Repair Area Overhead Reduction for Small Embedded SRAMs. 37-44 - Jochen Rivoir:
Statistical Linearity Calibration of Time-To-Digital Converters Using a Free-Running Ring Oscillator. 45-50 - Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang:
Histogram Based Testing Strategy for ADC. 51-54 - Yukiya Miura:
Detection of Interconnect Open Faults with Unknown Values by Ramp Voltage Application. 55-62 - Piet Engelke, Ilia Polian, Hans Manhaeve, Michel Renovell, Bernd Becker
Delta-IDDQ Testing of Resistive Short Defects. 63-68 - Masato Nakanishi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Yukiya Miura:
A BIC Sensor Capable of Adjusting IDDQ Limit in Tests. 69-74 - Alfredo Benso
ATPG for Dynamic Burn-In Test in Full-Scan Circuits. 75-82 - Nitin Yogi, Vishwani D. Agrawal:
Spectral RTL Test Generation for Gate-Level Stuck-at Faults. 83-88 - Tao Lv, Ling-Yi Liu, Yang Zhao, Huawei Li, Xiaowei Li:
An Observability Branch Coverage Metric Based on Dynamic Factored Use-Define Chains. 89-94 - Irith Pomeranz, Srinivas Patil, Praveen Parvathala:
A Functional Fault Model with Implicit Fault Effect Propagation Requirements. 95-102 - Shih-Chieh Wu, Chun-Yao Wang, Jan-an Hsieh:
The Potential and Limitation of Probability-Based Combinational Equivalence Checking. 103-108 - Jin-Fu Li, Chun-Hsien Wu:
Verification Methodology for Self-Repairable Memory Systems. 109-114 - Hiroki Nakahara
A Soft Error Tolerant LUT Cascade Emulator. 115-124 - Irith Pomeranz:
To Overtest Or Not To Overtest - More Questions Than Answers. 125 - Paul Wong, Jing Jiang:
How to Perform DFT Timing in Mixed Signal Designs, from 28 Hours to 7 Minutes. 126 - Kazuhiro Sakaguchi:
An Application of IDD Spectrum Testing Method to the Fault Analysis. 127 - Muhammad Aiman Mazlan, Ong Kein Wei, Cindy Phang Sim Sim:
iDEN Phone System Test: An Automation Approach. 128 - Masayoshi Yoshimura, Yusuke Matsunaga:
Development of practical ATPG tool with flexible interface. 129 - Greg Aldrich, Ron Press, Takeo Kobayashi, Tatsuo Sakajiri:
Mentor Graphics DFT to Navigate Nanometer Test Challenges. 130 - Hideaki Konishi, Michiaki Emori, Takahisa Hiraide:
The Application of BIST-Aided Scan Test for Real Chips. 131 - Anis Uzzaman, Brion L. Keller, Vivek Chickermane:
A Scalable Architecture for On-Chip Compression: Options and Trade-Offs. 132 - Fidel Muradali:
Practical Needs and Wants for Silicon Debug and Diagnosis. 135 - Xijiang Lin, Kun-Han Tsai, Chen Wang, Mark Kassab, Janusz Rajski, Takeo Kobayashi, Randy Klingenberg, Yasuo Sato, Shuji Hamada, Takashi Aikyo:
Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects. 139-146 - Anis Uzzaman, Mick Tegethoff, Bibo Li, Kevin McCauley, Shuji Hamada, Yasuo Sato:
Not all Delay Tests Are the Same - SDQL Model Shows True-Time. 147-152 - Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Takeo Kobayashi, Janusz Rajski, Bruce Swanson, Darryl Walters, Yasuo Sato, Toshiharu Asaka, Takashi Aikyo:
At-Speed Testing with Timing Exceptions and Constraints-Case Studies. 153-162 - Chia Yee Ooi, Hideo Fujiwara:
A New Scan Design Technique Based on Pre-Synthesis Thru Functions. 163-168 - Sying-Jyan Wang
Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage. 169-174 - Irith Pomeranz, Sudhakar M. Reddy:
On the Replacement of Scan Chain Inputs by Primary Input Vectors. 175-182 - Biplab K. Sikdar
Study of N-Detectability in QCA Designs. 183-188 - Ming Li, Shiyi Xu, Jialin Cao, Feng Ran, Shiwei Ma:
A Design of Pipelined Carry-dependent Sum Adder With its Self-checking Structure. 189-194 - Naghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi:
ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs. 195-202 - Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy:
Interconnect Open Defect Diagnosis with Physical Information. 203-209 - Yasuo Sato, Kazushi Sugiura, Reisuke Shimoda, Yutaka Yoshizawa, Kenji Norimatsu, Masaru Sanada:
Defect Diagnosis - Reasoning Methodology. 209-214 - Lei Wang, Sandeep K. Gupta, Melvin A. Breuer:
Diagnosis of delay faults due to resistive bridges, delay variations and defects. 215-224 - Po-Chang Tsai, Sying-Jyan Wang
Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction. 225-230 - Yu Hu, Cheng Li, Jia Li, Yinhe Han, Xiaowei Li, Wei Wang, Hua-Wei Li, Laung-Terng Wang, Xiaoqing Wen:
Test data compression based on clustered random access scan. 231-236 - Jinkyu Lee, Nur A. Touba:
Efficiently Utilizing ATE Vector Repeat for Compression by Scan Vector Decomposition. 237-244 - Hongjoong Shin, Jiseon Park, Jacob A. Abraham:
A Statistical Digital Equalizer for Loopback-based Linearity Test of Data Converters. 245-250 - Maohsuan Chou, Jen-Chien Hsu, Chauchin Su:
A Digital BIST Methodology for Spread Spectrum Clock Generators. 251-254 - Hao-Chiao Hong
A Cost Effective Output Response Analyzer for \sum - \delta Modulation Based BIST Systems. 255-264 - Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer:
Test Generation for Weak Resistive Bridges. 265-272 - Michel Renovell, Mariane Comte, Ilia Polian, Piet Engelke, Bernd Becker
A Specific ATPG technique for Resistive Open with Sequence Recursive Dependency. 273-278 - YongJoon Kim, Myung-Hoon Yang, Youngkyu Park, Daeyeal Lee, Sungho Kang:
An Effective Test Pattern Generation for Testing Signal Integrity. 279-286 - Xiaogang Du, Nilanjan Mukherjee, Chris Hill, Wu-Tung Cheng, Sudhakar M. Reddy:
A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops. 287-292 - Armin Alaghi, Mahnaz Sadoughi Yarandi, Zainalabedin Navabi:
An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table Testing. 293-298 - Hideo Fujiwara, Jiaguang Sun, Krishnendu Chakrabarty
Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture. 299-306 - Shalabh Goyal, Abhijit Chatterjee, Yanan Shieh:
Enhanced A/D Converter Signal-to-Noise-Ratio Testing in the Presence of Sampling Clock Jitter. 307-312 - Chung-Yi Li, Chia-yuan Chou, Tsin-Yuan Chang:
A Self-Referred Clock Jitter Measurement Circuit in Wide Frequency Range. 313-317 - Jiun-Lang Huang:
A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter. 318-326 - Terumine Hayashi, Naotsugu Ikeda, Tsuyoshi Shinogi, Haruhiko Takase, Hidehiko Kita:
Low Power Oriented Test Modification and Compression Techniques for Scan Based Core Testing. 327-332 - Zhanglei Wang, Krishnendu Chakrabarty
An Efficient Test Pattern Selection Method for Improving Defect Coverage with Reduced Test Data Volume and Test Application Time. 333-338 - Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell:
Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICs. 339-348 - Koji Yamazaki, Yuzo Takamatsu:
Fanout-based fault diagnosis for open faults on pass/fail information. 349-353 - Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, Yuzo Takamatsu:
Diagnosis of Transistor Shorts in Logic Test Environment. 354-359 - Andreas Leininger, Ajay Khoche, Martin Fischer, Nagesh Tamarapalli, Wu-Tung Cheng, Randy Klingenberg, Wu Yang:
The Next Step in Volume Scan Diagnosis: Standard Fail Data Format. 360-368 - Louis Bushard, Nathan Chelstrom, Steven Ross Ferguson, Brion Keller:
DFT of the Cell Processor and its Impact on EDA Test Softwar. 369-374 - Masato Nakazato, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara:
Design for Testability of Software-Based Self-Test for Processors. 375-380 - Brian Foutz, Vivek Chickermane, Bing Li, Harry Linzer, Gary Kunselman:
Automation of IEEE 1149.6 Boundary Scan Synthesis in an ASIC Methodology. 381-388 - Kazuteru Namba, Hideo Ito:
Interleaving of Delay Fault Tes Data for Efficient Test Compression with Statistical Coding. 389-394 - Taweesak Reungpeerakul, Xiaoshu Qian, Samiha Mourad:
BCH-based Compactors of Test Responses with Controllable Masks. 395-401 - Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki:
Expansion of Convolutional Compactors over Galois Field. 401-408 - Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara:
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. 409-414 - Sanae Seike, Ken Namura, Yukio Ohya, Anis Uzzaman, Shinichi Arima, Dale Meehl, Vivek Chickermane, Azumi Kobayashi, Satoshi Tanaka, Hiroyuki Adachi:
Early Life Cycle Yield Learning for Nanometer Devices Using Volume Yield Diagnostics Analysis. 415-420 - Sverre Wichlund, Einar J. Aas:
Reducing Scan Test Data Volume and Time: A Diagnosis Friendly Finite Memory Compactor. 421-430 - Chunsheng Liu:
Testing Hierarchical Network-on-Chip Systems with Hard Cores Using Bandwidth Matching and On-Chip Variable Clocking. 431-436 - Jaan Raik
An External Test Approach for Network-on-a-Chip Switches. 437-442 - Ariel Sabiguero Yawelak, César Viho:
Plug once, test everything. 443-448
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