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17th NEWCAS 2019: Munich, Germany
- 17th IEEE International New Circuits and Systems Conference, NEWCAS 2019, Munich, Germany, June 23-26, 2019. IEEE 2019, ISBN 978-1-7281-1031-8
- Celal Erbay
, Salih Ergün
Random Number Generator Based on Micro-Scale Bio-electrochemical Cell System. 1-4 - Ayman Mohamed
FIR Feedback in Continuous- Time Incremental Sigma-Delta ADCs. 1-4 - Lionel Morel, Damien Couroussé
Idols with Feet of Clay: On the Security of Bootloaders and Firmware Updaters for the IoT. 1-4 - Katrin Hirmer, Klaus Hofmann:
Substrate Coupling in a Fully Integrated Three-State High Voltage Inverter. 1-4 - Naoki Ojima, Zule Xu, Tetsuya Iizuka:
A 0.0053-mm2 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS. 1-4 - Hugo Dinis
Design and validation of a six-antenna WPT system with tracking capabilites for biomedical devices. 1-4 - Grégory Calegari Marchesan, Everton Alceu Carara, Crístian Müller, Leonardo Londero de Oliveira:
GCoL - A General Co-simulator Applied to Wireless Sensor Networks and RTL Design. 1-4 - Johan Nguyen
Systematic Design of On-Chip Matching Networks for D-band Circuits. 1-4 - Atul Thakur, Sweta Agarwal, Shouri Chatterjee
A 900-MHz 1.25-dB Noise-Figure Differential-Output LNA with 12.5 dB/mW FoM. 1-4 - Ahmed Mamdouh, Mohamed M. Aboudina, Faisal Hussien, Ahmed Nader Mohieldin
An Ultra-Broad-Band Low-Distortion High-Efficiency Class-D Power Amplifier in 130nm CMOS Technology. 1-4 - Amir Bozorg, Robert Bogdan Staszewski:
Two-Fold Noise-Cancelling Low-Noise Amplifier in 28-nm CMOS. 1-4 - Sri Navaneeth Easwaran
3A Fault Tolerant Low Side Driver Circuit Design Using Design FMEA for Automotive Applications. 1-4 - Moritz Bärthel
SORN Arithmetic for MIMO Symbol Detection - Exploration of the Type-2 Unum Format. 1-4 - Sven Lange, Dominik Schröder, Christian Hedayat, Thomas Otto
Inductive Locating Method to Locate Miniaturized Wireless Sensors within Inhomogeneous Dielectrics. 1-4 - Stefan Schmickl, Thomas Faseth, Harald Pretl:
A 1.9-µW 7-GHz IR-UWB Transmitter with RF-Energy-Harvester in 180-nm CMOS for Battery-Less Bio-Sensors. 1-4 - Menna Mohsen, Lobna A. Said, Ahmed H. Madian, Ahmed S. Elwakil, Ahmed G. Radwan:
Using Meta-heuristic Optimization to Extract Bio-impedance Parameters from an Oscillator Circuit. 1-4 - Ali Zeineddine, Stéphane Paquelet, Amor Nafkha
Efficient Arbitrary Sample Rate Conversion for Multi-Standard Digital Front-Ends. 1-4 - Elias Soleiman, Dang-Kièn Germain Pham, Chadi Jabbour, Patricia Desgreys, Mahmoud Kamarei:
Physically-Derived 3-Box Power Amplifier Model. 1-4 - Dustin Peterson, Oliver Bringmann:
Power-Gating Models for Rapid Design Exploration. 1-4 - Dongyang Yan, Mark Ingels, Giovanni Mangraviti, Yao Liu, Bertrand Parvais
Design of a 28 GHz differential GaAs power amplifier with capacitive neutralization for 5G mmwave applications. 1-4 - Ali Al Shakoush, Estelle Lauga-Larroze, Serge Subias, Thierry Taris, Florence Podevin, Sylvain Bourdel:
Low Complexity Architecture of N-Path Mixers for Low Power Application. 1-4 - Leonardo B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt
Exploring Schmitt Trigger Circuits for Process Variability Mitigation. 1-4 - Pragoti Pran Bora, David Borggreve
A 0.8 V Low-Power 3rd order Sigma-Delta Modulator in 22 nm FDSOI CMOS Process for Sensor Interfaces. 1-4 - Zhiwei Zong
A 22-29 GHz Voltage-Biased LC-VCO with Suppressed Flicker Noise over Tuning Range in 22nm FD-SOI. 1-4 - Dieison Soares Silveira
Energy Savings with Non-Volatile Memory System for High Definition Video Encoders. 1-4 - Joe Bachi
New Analytical Boundary Condition for Optimized Outphasing PA Design. 1-4 - Pavel Afanasyev, Prasidh Ramabadran, Ronan Farrell, John Dooley:
Nonlinearity Modeling of Chireix Outphasing Power Combiner Under Amplitude Imbalance. 1-4 - Alexandra Listl, Daniel Mueller-Gritschneder
MAGIC: A Wear-leveling Circuitry to Mitigate Aging Effects in Sense Amplifiers of SRAMs. 1-4 - Zakaria El Alaoui Ismaili
A Comparison of Frequency Synthesizers Up to 25 GHz for 130 nm CMOS Implementation. 1-4 - Mingzhu Long, Xiang Xie, Guolin Li, Zhihua Wang:
Wireless Capsule Endoscopic Image Enhancement Method Based on Histogram Correction and Unsharp Masking in Wavelet Domain. 1-4 - Mohammed E. Fouda, Ahmed M. Eltawil
Activated Current Sensing Circuit for Resistive Neuromorphic Networks. 1-4 - Milad Omrani Tamrin, Sébastien Henwood, Jean-François Dubois, Jean-Jules Brault, Saad Chidami, Samuel-Jean Bassetto:
Using deep learning approaches to overcome limited dataset issues within semiconductor domain. 1-4 - Ata Khorami, Roghayeh Saeidi, Mohammad Sharifkhani, Nima Taherinejad:
An Ultra Low-power Low-offset Double-tail Comparator. 1-4 - Sami Ur Rehman, Ali Ferchichi, Mohammad Mahdi Khafaji, Corrado Carta
A 2.8 pJ/bit 10 Gb/s Delayed-Phase-Select 2-bit Pulsewidth Modulator in 45-nm SOI CMOS. 1-4 - Amit Sangwan
CDM-based 4-Channel Digital Beamforming Transmitter Using a Single DAC. 1-4 - Marco A. Saif
A 34-fJ/bit 20-Gb/s 1/8-rate Charge-Steering DFE for IoT Applications. 1-4 - Frédéric Hameau, Jennifer Zaini, Thierry Taris, Dominique Morche, Baudouin Martineau, Patrick Audebert:
New Design Opportunities exploiting FDSOI technology for RF Power Amplifier and LNA design. 1-4 - Guilherme Paim
Maximizing the Power-Efficiency of the Approximate Pruned Modified Rounded DCT Exploiting Approximate Adder Compressors. 1-4 - Firat Celik, Ayca Akkaya, Armin Tajalli, Yusuf Leblebici:
ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links. 1-4 - Ludwig Karsthof, Mingjie Hao, Jochen Rust
Ultra Low Latency Implementation of Robust Channel Estimation and Equalization for Industrial Wireless Communication Systems. 1-4 - Fakhreddine Ghaffari, Khoa Le, David Declercq:
The Probabilistic Finite Alphabet Iterative Decoder for Low-Density Parity-Check Codes. 1-4 - Shantanu Mehta, Anthony G. Scanlan
A Tri-level Current-Steering DAC Design with Improved Output-Impedance Related Dynamic Performance. 1-4 - Shao-Yung Lu, I-Feng Wu, Ying-Chih Liao, Yu-Te Liao
Wirelessly-Powered Printed Temperature Sensor with an Ultra-Low-Power and High-Sensitivity CMOS Readout IC. 1-4 - Leonhard Klein, Antonios Nikas, Bijoy Kundu, Matthias Völker:
A 300MS/s 10bit SAR with loop-embedded input buffer for a photonic system. 1-4 - Michael Pronath:
Challenges in Statistical Analysis: Yesterday, Today, and Tomorrow: (Invited Paper). 1-4 - Christian Hangmann, Christian Hedayat, Ulrich Hilleringmann:
Designing Mixed-Signal PLLs regarding Multiple Requirements taking Non-Ideal Effects into Account. 1-4 - Kaya Demir, Salih Ergün
Analysis of Random Number Generators Based on Fibonacci-Galois Ring Oscillators. 1-4 - Roman Sotner, Lukas Langhammer, Jan Jerabek
Fractional-Order Asymptotical Phase Shifter with Flat Magnitude Response. 1-4 - Antonio De Vita, Gian Domenico Licciardo
µW Pre-processing Unit for Virtual Sensors Based on Tri-axial Smart Accelerometers. 1-4 - Merna Roshdy, Mohammed F. Tolba, Lobna A. Said, Ahmed H. Madian, Ahmed G. Radwan:
Generic Hardware of Fractional Order Multi-Scrolls Chaotic Generator Based on FPGA. 1-4 - Zhuoyi Sun, Yingdan Li, Hanjun Jiang, Zhihua Wang:
An RNN-based Speech Enhancement Method for a Binaural Hearing Aid System. 1-4 - Eugene Koskin, Pierre Bisiaux, Dimitri Galayko, Elena Blokhina
All-Digital Phase-Locked Loop Arrays: Investigation of Synchronisation and Jitter Performance through FPGA Prototyping. 1-4 - Jochen Rust
Adaptive Bivariate Function Generation based on Chebyshev-Polynomials. 1-4 - Yue Li, Fei Yuan:
Data-Transition Decision Feedback Equalizer with Edge-Emphasis Taps and Raised References. 1-4 - Isam Gharib, Mohamad Sawan:
High-efficiency LED Driver for Short Fluorophores Lifetime Biosensing Applications. 1-4 - Weiwei Wu, Shouyi Yin, Fengbin Tu, Leibo Liu, Shaojun Wei:
MoNA: Mobile Neural Architecture with Reconfigurable Parallel Dimensions. 1-4 - Ayman A. Atallah, Ghaith Bany Hamad, Otmane Aït Mohamed, Mounir Boukadoum:
High-Level Availability Analysis of FPGA-Based Time-Sensitive Networks. 1-4 - Fredrik Tillman, Sven Mattisson:
Going from a 5G Vision to real Implementation. 1-4 - Xinyan Tang
Design of A D-band Transformer-Based Neutralized Class-AB Power Amplifier in Silicon Technologies. 1-4 - Hassen Aziza, Mathieu Moreau
A Capacitor-Less CMOS Neuron Circuit for Neuromemristive Networks. 1-4 - Salih Ergün
Estimating the Unknown Parameters of a Random Number Generator Based on a Chaotic Jerk System. 1-4 - Aymeric Panglosse, Philippe Martin-Gonthier, Olivier Marcelot, Cédric Virmontois, Olivier Saint-Pé, Pierre Magnan:
Dark Count Rate Modeling in Single-Photon Avalanche Diodes for Space LIDAR Applications. 1-4 - Kun-Chih Chen
A Low-Complex Compressive Sensing Based Thermal Sensor Placement for Multicore Systems. 1-4 - Takeshi Kumaki, Tomohiro Fujita, Takeshi Ogura, P. S. Venugopala:
Distributed Embedding Approach for Max-Plus Algebra-Based Morphological Wavelet Transform Watermarking. 1-4 - Yan Chen, Jing Zhang, Yingjie Zhang, Renyuan Zhang, Mutsumi Kimura, Yasuhiko Nakashima:
A Programmable Calculation Unit Employing Memcapacitor-based Neuromorphic Circuit. 1-4 - Hamza Landari, Mourad Roudjane, Younès Messaddeq
Pseudo-Continuous Flow System for Dopamine and Ascorbic Acid Detection Based on FTIR-Spectrometery. 1-4 - Mateusz Rzymowski, Kamil Trzebiatowski
DoA Estimation Using Reconfigurable Antennas in Millimiter-Wave Frequency 5G Systems. 1-4 - Wei Chu, Shi-Yu Huang:
A Cell-Based Wide-Frequency-Range DLL Supporting Fast Frequency Scaling. 1-4 - Shiyong Zhang, Penghui Zheng, Jianxing Xu, Rong Wang, Yang Huang, Xiaodong Tong:
A 15 - 34 GHz Robust GaN based Low-Noise Amplifier with 0.8dB Minimum Noise Figure. 1-4 - Jin-Tai Yan, Chia-Heng Yen:
Construction of Delay-Driven GNR Routing Tree. 1-4 - Breytner Fernández-Mesa, Liliana Andrade, Frédéric Pétrot:
Electronic System Level Design of Heterogeneous Systems: a Motor Speed Control System Case Study. 1-4 - Nima Lotfi
An UWB 18.5 GS/s Sampling Front-End for a 74 GS/s 5-bit ADC in 22nm FDSOI. 1-4 - Markus Hefele
Integrated multipurpose analog front-end for electrochemical ISFET sensors. 1-4 - Lukas Straczek, Furkan Ercan
A Novel Offset and 1/f Noise Compensated Single-Slope ADC with Reduced Hardware Effort. 1-4 - Zhong Gao
28 GHz Quadrature Frequency Generation Exploiting Injection-Locked Harmonic Extractors for 5G Communications. 1-4 - Ibrahim Tastan, Salih Ergün
A Robust Random Number Generator Based on Chaotic Ring Oscillators. 1-4 - Vitor F. Silva, Hugo Dinis
Shared wireless link co-design for implantable device with far-field wireless power transfer. 1-4 - Salman Anwar Khokhar, Amad Ul Hassen:
Synthesis of Approximate Logic on Memristive Crossbars. 1-4 - Florian Wilde
On the Confidence in Bit-Alias Measurement of Physical Unclonable Functions. 1-4 - Brunno Abreu
Exploring Motion Vector Cost with Partial Distortion Elimination in Sum of Absolute Differences for HEVC Integer Motion Estimation. 1-4 - Siqi Wang, Morgan Roger, Caroline Lelandais-Perrault:
Optimization of a pruned 2-D Digital Predistortion Model Structure for Power Amplifiers Linearization. 1-4 - Markus Stadelmayer
A 0.5-V 180-nm CMOS Switched-Capacitor Temperature Sensor with 319 nJ/measurement. 1-4 - Aleksandr Gusev, Dmitry Osipov, Steffen Paul:
Multi-step capacitor switching scheme for low-power SAR ADC. 1-4 - Eva Schulte Bocholt, Leo Rolff, Ralf Wunderlich, Stefan Heinen:
Self-Calibrating Digital-to-Time Converter in CMOS for Advanced Control in Smart Gate Drivers. 1-4 - Loïc Massin
Towards accurate camera-less eye tracker using instrumented contact lens. 1-4 - Mingjie Hao, Ludwig Karsthof, Jochen Rust
Enhanced Symbol Synchronization for Multi-User High Reliable Dynamic Industrial Wireless Communication. 1-4 - Alexandre Giry, Eric Mercier, Ayssar Serhan, Damien Parat, Pascal Reynier, R. Berro, R. Mourot, C. De Ranter, P. Indirayanti, M. Borremans:
A 2.5GHz LTE Doherty Power Amplifier in SOI-CMOS Technology. 1-4 - Imran Bashir
A Verilog-A Model of the Shuttle of an Electron in a Two Quantum-Dot System. 1-4 - Amin Aghighi, Jacob Atkinson, Nickolas Bybee, Stuart Anderson, Mitchell Crane, Anthony Bailey, Reuben Morell, Ahmed Hassanin, Armin Tajalli:
CMOS Amplifier Design Based on Extended $g_{m}/I_{D}$ Methodology. 1-4 - Ilia Polian:
Fault Attacks on Cryptographic Circuits. 1-4 - Ghouthi B. Hacene, Vincent Gripon, Nicolas Farrugia, Matthieu Arzel
Efficient Hardware Implementation of Incremental Learning and Inference on Chip. 1-4 - Grégory Calegari Marchesan, Everton Alceu Carara, Marcelo Serrano Zanetti, Leonardo Londero de Oliveira:
Exploring the Training and Execution Acceleration of a Neural Network in a Reconfigurable General-purpose Processor for Embedded Systems. 1-4 - Nima Taherinejad, Théophile Delaroche, David Radakovits, Shahriar Mirabbasi:
A Semi-Serial Topology for Compact and Fast IMPLY-based Memristive Full Adders. 1-4 - Dmitry Osipov, Aleksandr Gusev, Steffen Paul:
First Order Fully Passive Noise-Shaping SAR ADC Architecture with NTF Zero close to One. 1-4 - Elias de Almeida Ramos, João Carlos Britto Filho, Ricardo A. L. Reis:
Cryptography by Synchronization of Hopfield Neural Networks that Simulate Chaotic Signals Generated by the Human Body. 1-4 - Sami Ur Rehman, Mohammad Mahdi Khafaji, Ali Ferchichi, Corrado Carta
A 0.93 pJ/bit Controlled Capacitor-Charge 2-bit Pulsewidth Demodulator in 45-nm RFSOI CMOS. 1-4 - Peng Cao, Zhiyuan Liu, Jingjing Guo, Haoyu Pang, Jiangping Wu, Jun Yang:
Accurate and Efficient Interdependent Timing Model for Flip-Flop in Wide Voltage Region. 1-4
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last updated on 2024-11-15 19:43 CET by the dblp team
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