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Eugene Koskin
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2020 – today
- 2024
- [c13]Nicola Mariella, Albert Akhriev, Francesco Tacchino, Christa Zoufal, Juan Carlos Gonzalez-Espitia, Benedek Harsanyi, Eugene Koskin, Ivano Tavernelli, Stefan Woerner, Marianna Rapsomaniki, Sergiy Zhuk, Jannis Born:
Quantum Theory and Application of Contextual Optimal Transport. ICML 2024 - [i2]Dmytro Mishagli, Eugene Koskin, Elena Blokhina:
Gate-Level Statistical Timing Analysis: Exact Solutions, Approximations and Algorithms. CoRR abs/2401.03588 (2024) - [i1]Nicola Mariella, Albert Akhriev, Francesco Tacchino, Christa Zoufal, Juan Carlos Gonzalez-Espitia, Benedek Harsanyi, Eugene Koskin, Ivano Tavernelli, Stefan Woerner, Marianna Rapsomaniki, Sergiy Zhuk, Jannis Born:
Quantum Theory and Application of Contextual Optimal Transport. CoRR abs/2402.14991 (2024) - 2023
- [j5]Ali Esmailiyan, Elena Blokhina
, Dennis Andrade-Miceli, Eoin Faust, Panagiotis Giounanlis
An On-Chip Picoampere-Level Leakage Current Sensor for Quantum Processors in 22-nm FD-SOI CMOS. IEEE Trans. Circuits Syst. II Express Briefs 70(6): 1861-1865 (2023) - 2021
- [j4]Eugene Koskin
All Digital Phase-Locked Loop Networks for Clock Generation and Distribution: Network Stability, Convergence and Performance. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 406-415 (2021) - [j3]Eugene Koskin
Jitter Optimisation in a Generalised All-Digital Phase-Locked Loop Model. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 77-81 (2021) - 2020
- [c12]Pierre Bisiaux, Elena Blokhina
Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process. ECCTD 2020: 1-5 - [c11]Eugene Koskin, Pierre Bisiaux, Dimitri Galayko, Elena Blokhina
FPGA Validation of Event-Driven ADPLL. ECCTD 2020: 1-4 - [c10]Eugene Koskin, Maksim Balakin, Nikita Ryskin, Dimitri Galayko, Elena Blokhina
Synchronisation in Noisy PLL Networks: Time Domain Model and its Analysis. ECCTD 2020: 1-4 - [c9]Andrii Sokolov
Simulation Methodology for Electron Transfer in CMOS Quantum Dots. ICCS (6) 2020: 650-663 - [c8]Panagiotis Giounanlis, Andrii Sokolov
Electrostatic Control and Entanglement of CMOS Position-Based Qubits. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c7]Dmytro Mishagli, Eugene Koskin, Elena Blokhina
Path-Based Statistical Static Timing Analysis for Large Integrated Circuits in a Weak Correlation Approximation. ISCAS 2019: 1-5 - [c6]Eugene Koskin, Pierre Bisiaux, Dimitri Galayko, Elena Blokhina
All-Digital Phase-Locked Loop Arrays: Investigation of Synchronisation and Jitter Performance through FPGA Prototyping. NEWCAS 2019: 1-4 - 2018
- [j2]Eugene Koskin
A Concept of Synchronous ADPLL Networks in Application to Small-Scale Antenna Arrays. IEEE Access 6: 18723-18730 (2018) - [j1]Eugene Koskin
Generation of a Clocking Signal in Synchronized All-Digital PLL Networks. IEEE Trans. Circuits Syst. II Express Briefs 65-II(6): 809-813 (2018) - [c5]Eugene Koskin, Dimitri Galayko, Elena Blokhina
Averaging Techniques for the Analysis of Event Driven Models of All Digital PLLs. ISCAS 2018: 1-5 - 2017
- [c4]Eugene Koskin, Dimitri Galayko, Orla Feely, Elena Blokhina
Semianalytical model for high speed analysis of all-digital PLL clock-generating networks. ISCAS 2017: 1-4 - 2016
- [c3]Eugene Koskin:
Discrete-time modelling and experimental validation of an all-digital PLL for clock-generating networks. ICECS 2016: 434-435 - [c2]Eugene Koskin, Elena Blokhina
Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks. NEWCAS 2016: 1-4 - 2015
- [c1]Eugene Koskin, Dimitri Galayko, Orla Feely
Mode-locking in a network of kuramoto-like oscillators. IJCNN 2015: 1-6
Coauthor Index
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