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Yasuhiro Takahashi
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2020 – today
- 2024
- [j32]Toshiyuki Inoue
, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura:
A burst-mode receiver with quick response and high consecutive identical digit tolerance for advanced intra-vehicle optical networks. Microelectron. J. 145: 106120 (2024) - [j31]Toshiyuki Inoue
A 16-Channel Optical Receiver Circuit for a Multicore Fiber-Based Co-Packaged Optics Module in a 65-nm CMOS Chip. IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2514-2518 (2024) - [c58]Yasuhiro Takahashi
A 25-Gb/s Active Feedback Transimpedance Amplifier in 65-nm CMOS. ICEIC 2024: 1-4 - [c57]Koji Tominaga, Yasuhiro Takahashi
Low-Power, 25-Gb/s Active Voltage Current Feedback Transimpedance Amplifier in 65-nm CMOS. ICEIC 2024: 1-4 - [c56]Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura:
A Small-Area and Low-EPB Inductive-Peaking VCSEL Driver for a 65-nm CMOS Chip. SOCC 2024: 1-6 - 2023
- [j30]Daisuke Ito, Yasuhiro Takahashi
10Gb/s burst-mode driver circuit with on-chip bias switch for in-Vehicle optical networks. IEICE Electron. Express 20(14): 20230238 (2023) - [j29]Yasuhiro Takahashi
Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process. IEICE Electron. Express 20(18): 20230339 (2023) - [c55]Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi
High-Speed, Low-Power, and Small-Area Optical Receiver in 65-nm CMOS. ASICON 2023: 1-2 - [c54]Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi
A 4×32-Gb/s VCSEL Driver with Adaptive Feedforward Equalization in 65-nm CMOS. ICECS 2023: 1-4 - [c53]Daisuke Ito, Yasuhiro Takahashi
4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS. ISOCC 2023: 13-14 - 2022
- [j28]Yuki Takeuchi
Divide-and-conquer verification method for noisy intermediate-scale quantum computation. Quantum 6: 758 (2022) - [c52]Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi
Capacitor Under Pad for Small Area Integration of High-Speed Signal-to-Differential Amplifier. ICEIC 2022: 1-4 - [c51]Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi
A Burst-Mode TIA with Automatic Power Saving and DC Wander Reduction in 65-nm CMOS. ICECS 2022 2022: 1-4 - [c50]Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi
A 28-Gb/s VCSEL Driver with Variable Output Impedance in 65-nm CMOS. MWSCAS 2022: 1-4 - [c49]Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi
A Small-Area Integration of Optical Receiver Using Multi-Layer Inductors and Capacitor-Under-Pad. MWSCAS 2022: 1-4 - 2021
- [j27]Câncio Monteiro
Ultra-Low-Power FinFETs-Based TPCA-PUF Circuit for Secure IoT Devices. Sensors 21(24): 8302 (2021) - [j26]Yasuhiro Takahashi, Seiichiro Tani:
Power of uninitialized qubits in shallow quantum circuits. Theor. Comput. Sci. 851: 129-153 (2021) - [j25]Yasuhiro Takahashi, Yuki Takeuchi, Seiichiro Tani
Classically simulating quantum circuits with local depolarizing noise. Theor. Comput. Sci. 893: 117-132 (2021) - [c48]Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi
A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks. ICECS 2021: 1-6 - 2020
- [j24]Hiroki Koyasu, Yasuhiro Takahashi
Performance and Security Evaluation of S-Box Using Current-Pass Optimized Symmetric Pass Gate Adiabatic Logic. SN Comput. Sci. 1(4): 199 (2020) - [j23]Yasuhiro Takahashi
Quasi-Adiabatic SRAM Based Silicon Physical Unclonable Function. SN Comput. Sci. 1(5): 237 (2020) - [c47]Kohei Ogura, Yasuhiro Takahashi
Special Session: An Adiabatic Logic Based Silicon Physical Unclonable Function. ICCD 2020: 29-32 - [c46]Yasuhiro Takahashi
Message from the Technical Program Chairs iSES 2020. iSES 2020: xvi - [c45]Yasuhiro Takahashi, Yuki Takeuchi, Seiichiro Tani
Classically Simulating Quantum Circuits with Local Depolarizing Noise. MFCS 2020: 83:1-83:13 - [i6]Yasuhiro Takahashi, Yuki Takeuchi, Seiichiro Tani:
Classically Simulating Quantum Circuits with Local Depolarizing Noise. CoRR abs/2001.08373 (2020) - [i5]Yuki Takeuchi, Yasuhiro Takahashi, Seiichiro Tani:
Efficiently generating ground states is hard for postselected quantum computation. CoRR abs/2006.12125 (2020)
2010 – 2019
- 2019
- [j22]Mei Han
Non-floating and low-power adiabatic logic circuit. IEICE Electron. Express 16(17): 20190400 (2019) - [j21]Hiroki Koyasu, Yasuhiro Takahashi
Current Pass Optimized Symmetric Pass Gate Adiabatic Logic for Cryptographic Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 12: 50-52 (2019) - [c44]Xiangyu Chen
Design of a CMOS Broadband Transimpedance Amplifier with Floating Active Inductor. ISVLSI 2019: 230-234 - [c43]Hiroki Koyasu, Yasuhiro Takahashi
Evaluation of Power Analysis Attacks on Cryptographic Circuit Using Adiabatic Logic. ISVLSI 2019: 409-413 - [c42]Yasuhiro Takahashi
Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function. ISVLSI 2019: 443-446 - 2018
- [c41]Câncio Monteiro
Low Power Source Biased Semi-Adiabatic Logic Circuit for IoT Devices. ISPACS 2018: 43-47 - [c40]Ryosuke Ohashi, Yasuhiro Takahashi
A New Adiabatic Logic without Charge Sharing Gate for Cryptographic Devices. ISPACS 2018: 117-121 - [c39]Takumi Fukuura, Yasuhiro Takahashi
5.6 GHz, 61.7 dBΩ Transimpedance Amplifier Using Active Inductor in Shunt and Series Peaking Techniques. ISPACS 2018: 392-395 - [c38]Ryo Tagawa, Yasuhiro Takahashi
5.3 GHz, 69.6 dBΩ Transimpedance Amplifier with Negative Impedance Converter. ISPACS 2018: 396-400 - [c37]Yasuhiro Takahashi, Seiichiro Tani
Power of Uninitialized Qubits in Shallow Quantum Circuits. STACS 2018: 57:1-57:13 - 2017
- [c36]Yuya Kojima, Toshikazu Sekine, Yasuhiro Takahashi
Generalized indirect S-parameter measurement method of n-ports circuit using T-parameter of (m, n)-ports fixture. ECCTD 2017: 1-4 - [c35]Mei Han
Low power Adiabatic Logic based on 2PC2AL. ICICDT 2017: 1-4 - [c34]Yasuhiro Takahashi
Operational amplifier based LC resonant circuit for adiabatic logic. MIXDES 2017: 110-113 - 2016
- [j20]Yasuhiro Takahashi, Seiichiro Tani
Collapse of the Hierarchy of Constant-Depth Exact Quantum Circuits. Comput. Complex. 25(4): 849-881 (2016) - [j19]Yasuhiro Takahashi, Seiichiro Tani, Takeshi Yamazaki, Kazuyuki Tanaka:
Commuting quantum circuits with few outputs are unlikely to be classically simulatable. Quantum Inf. Comput. 16(3&4): 251-270 (2016) - [i4]Yasuhiro Takahashi, Seiichiro Tani:
Shallow Quantum Circuits with Uninitialized Ancillary Qubits. CoRR abs/1608.07020 (2016) - [i3]Yuki Takeuchi, Yasuhiro Takahashi:
Ancilla-driven instantaneous quantum polynomial time circuit for quantum supremacy. CoRR abs/1611.00510 (2016) - 2015
- [j18]Yasuhiro Takahashi
SPICE model of memristive device using Tukey window function. IEICE Electron. Express 12(5): 20150149 (2015) - [j17]Kazunari Kato, Yasuhiro Takahashi
Two phase clocked subthreshold adiabatic logic circuit. IEICE Electron. Express 12(20): 20150695 (2015) - [j16]Câncio Monteiro
Low-power secure S-box circuit using charge-sharing symmetric adiabatic logic for advanced encryption standard hardware design. IET Circuits Devices Syst. 9(5): 362-369 (2015) - [c33]Yasuhiro Takahashi, Seiichiro Tani
Commuting Quantum Circuits with Few Outputs are Unlikely to be Classically Simulatable. COCOON 2015: 223-234 - [c32]Noboru Maeda, Shinji Fukui, Toshikazu Sekine, Yasuhiro Takahashi
An improved estimation method of 4 port S-parameters with 2 port measurements. ECCTD 2015: 1-4 - [c31]Rui Manuel de Oliveira Amaral Sarmento, Yasuhiro Takahashi
Power saving analysis of step-down buck converter using adiabatic switching principle. ISPACS 2015: 346-350 - [c30]Kazunari Kato, Yasuhiro Takahashi
A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic. NEWCAS 2015: 1-4 - 2014
- [j15]Yasuhiro Takahashi, Takeshi Yamazaki, Kazuyuki Tanaka:
Hardness of classically simulating quantum circuits with unbounded Toffoli and fan-out gates. Quantum Inf. Comput. 14(13-14): 1149-1164 (2014) - [c29]Câncio Monteiro
Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation. APCCAS 2014: 121-124 - [c28]Kazunari Kato, Yasuhiro Takahashi
Skew tolerance analysis and layout design of 4×4 multiplier using two phase clocking subthreshold adiabatic logic. APCCAS 2014: 495-498 - [c27]Haruki Ogata, Yasuhiro Takahashi
Power dissipation analysis of memristor for low power integrated circuit applications. APCCAS 2014: 627-630 - [c26]Kazunari Kato, Yasuhiro Takahashi
Two phase clocking subthreshold adiabatic logic. ISCAS 2014: 598-601 - [c25]Câncio Monteiro
An LSI implementation of a bit-parallel cellular multiplier over GF(24) using secure charge-sharing symmetric adiabatic logic. ISCAS 2014: 826-829 - [c24]Câncio Monteiro
Process variation verification of low-power secure CSSAL AES S-box circuit. MWSCAS 2014: 21-24 - [i2]Yasuhiro Takahashi, Seiichiro Tani, Takeshi Yamazaki, Kazuyuki Tanaka:
Commuting Quantum Circuits with Few Outputs are Unlikely to be Classically Simulatable. CoRR abs/1409.6792 (2014) - 2013
- [j14]Câncio Monteiro
Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level. Microelectron. J. 44(6): 496-503 (2013) - [j13]Thomas Hobiger
Dissemination of UTC(NICT) by Means of QZSS. IEEE Trans. Instrum. Meas. 62(6): 1537-1544 (2013) - [c23]Yasuhiro Takahashi, Seiichiro Tani
Collapse of the Hierarchy of Constant-Depth Exact Quantum Circuits. CCC 2013: 168-178 - [c22]Noboru Maeda, Shinji Fukui, Toshikazu Sekine, Yasuhiro Takahashi:
An estimation method for the 3 port S-parameters with 1 port measurements. ECCTD 2013: 1-4 - [c21]Câncio Monteiro
Low power secure CSSAL bit-parallel multiplier over GF(24) in 0.18μm CMOS technology. ECCTD 2013: 1-4 - [c20]Câncio Monteiro
DPA resistance of charge-sharing symmetric adiabatic logic. ISCAS 2013: 2581-2584 - [c19]Yasuhiro Takahashi, Takeshi Yamazaki, Kazuyuki Tanaka:
Hardness of Classically Simulating Quantum Circuits with Unbounded Toffoli and Fan-Out Gates. MFCS 2013: 801-812 - [c18]Câncio Monteiro
Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks. TSP 2013: 732-736 - 2012
- [j12]Nazrul Anuar Nayan
LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier. Microelectron. J. 43(4): 244-249 (2012) - [c17]Yuki Urata, Yasuhiro Takahashi
A low-power sense amplifier for adiabatic memory using memristor. APCCAS 2012: 112-115 - [c16]Yasuhiro Takahashi
2PCDAL: Two-phase clocking dual-rail adiabatic logic. APCCAS 2012: 124-127 - [c15]Yasuhiro Takahashi
Power-saving analysis of adiabatic logic in subthreshold region. ISPACS 2012: 590-594 - 2011
- [c14]Hides Jamima, Yasuhiro Takahashi
Low-power adiabatic SRAM. ISPACS 2011: 1-4 - [c13]Câncio Monteiro
Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card. ISPACS 2011: 1-5 - [c12]Yasuhiro Takahashi, Akinori Maeda, Mitsuhiro Ogura:
Actual implementation of multi domain test: Further reduction of cost of test. ITC 2011: 1-8 - [c11]Yasuhiro Takahashi, Akinori Maeda:
Multi Domain Test: Novel test strategy to reduce the Cost of Test. VTS 2011: 303-308 - [i1]Yasuhiro Takahashi, Seiichiro Tani:
Constant-Depth Exact Quantum Circuits for the OR and Threshold Functions. CoRR abs/1112.6063 (2011) - 2010
- [j11]Yasuhiro Takahashi, Seiichiro Tani, Noboru Kunihiro:
Quantum addition circuits and unbounded fan-out. Quantum Inf. Comput. 10(9&10): 872-890 (2010) - [c10]Yasuhiro Takahashi:
Simple Sets of Measurements for Universal Quantum Computation and Graph State Preparation. TQC 2010: 26-34 - [c9]Nazrul Anuar
4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR. VLSI-SoC 2010: 364-368
2000 – 2009
- 2009
- [j10]Yasuhiro Takahashi:
Quantum Arithmetic Circuits: A Survey. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(5): 1276-1283 (2009) - [c8]Nazrul Anuar
4-bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: A comparison with static CMOS. ECCTD 2009: 65-68 - [c7]Kazunari Kato, Yasuhiro Takahashi
A new horizontal and vertical common subexpression elimination method for multiple constant multiplication. ICECS 2009: 124-127 - [c6]Nazrul Anuar
Fundamental logics based on two phase clocked adiabatic static CMOS logic. ICECS 2009: 503-506 - [c5]Nazrul Anuar
Two phase clocked adiabatic static CMOS logic. SoC 2009: 83-86 - 2008
- [j9]Yasuhiro Takahashi, Noboru Kunihiro:
A fast quantum circuit for addition with few qubits. Quantum Inf. Comput. 8(6): 636-649 (2008) - 2007
- [j8]Yasuhiro Takahashi
A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 µm Standard CMOS Library. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(7): 1376-1383 (2007) - [j7]Yasuhiro Takahashi, Toshikazu Sekine, Michio Yokoyama:
VLSI Implementation of a 4 x 4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic. IEICE Trans. Electron. 90-C(10): 2002-2006 (2007) - [j6]Yasuhiro Takahashi, Noboru Kunihiro, Kazuo Ohta:
The quantum fourier transform on a linear nearest neighbor architecture. Quantum Inf. Comput. 7(4): 383-391 (2007) - 2006
- [j5]Yasuhiro Takahashi, Noboru Kunihiro:
A quantum circuit for shor's factoring algorithm using 2n + 2 qubits. Quantum Inf. Comput. 6(2): 184-192 (2006) - [c4]Yasuhiro Takahashi
2PADCL: Two Phase drive Adiabatic Dynamic CMOS Logic. APCCAS 2006: 1484-1487 - 2005
- [j4]Yasuhiro Takahashi, Noboru Kunihiro:
A linear-size quantum circuit for addition with no ancillary qubits. Quantum Inf. Comput. 5(6): 440-448 (2005) - [c3]Yasuhiro Takahashi
New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression elimination. ISCAS (2) 2005: 1445-1448 - 2003
- [j3]Yasuhiro Takahashi, Kei-ichi Konta, Kazukiyo Takahashi, Michio Yokoyama, Kazuhiro Shouno, Mitsuru Mizunuma:
Carry Propagation Free Adder/Subtracter Using Adiabatic Dynamic CMOS Logic Circuit Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(6): 1437-1444 (2003) - [c2]Yasuhiro Takahashi, Yasuhito Kawano, Masahiro Kitagawa:
On the computational power of constant-depth quantum circuits with gates for addition. IEEE Congress on Evolutionary Computation 2003: 154-161 - 2002
- [c1]Yasuhiro Takahashi, Kohji Dohsaka, Kiyoaki Aikawa:
An efficient dialogue control method using decision tree-based estimation of out-of-vocabulary word attributes. INTERSPEECH 2002: 813-816
1990 – 1999
- 1992
- [j2]Tohru Hoshi, Yasuhiro Takahashi, Kenjiro Mori:
An integrated multimedia desktop communication and collaboration platform for broadband ISDN: the broadband ISDN group tele-working system. Comput. Commun. Rev. 22(3): 14-15 (1992) - [j1]Tohru Hoshi, Kenjiro Mori, Yasuhiro Takahashi, Yoshiyuki Nakayama, Takeshi Ishizaki:
B-ISDN Multimedia Communication and Collaboration Platform Using Advanced Video Workstations to Support Cooperative Work. IEEE J. Sel. Areas Commun. 10(9): 1403-1412 (1992)
Coauthor Index
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