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"LSI implementation of a low-power 4×4-bit array two-phase clocked ..."

Nazrul Anuar Nayan, Yasuhiro Takahashi, Toshikazu Sekine (2012)

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DOI: 10.1016/J.MEJO.2011.12.013

access: closed

type: Journal Article

metadata version: 2020-02-22

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Nazrul Anuar Nayan, Yasuhiro Takahashi, Toshikazu Sekine:
LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier. Microelectron. J. 43(4): 244-249 (2012)

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