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Yann Civale
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2010 – 2019
- 2013
- [c4]Yann Civale, Herman Meynen, Ranjith S. E. John, Peng-Fei Fu, Craig R. Yeakle, Sheng Wang, Stefan Krausse, Thomas Rapps, Stefan Lutter:
Cost-effective temporary bonding and debonding material solution towards high-volume manufacturing 2.5D/3D through-silicon via integrated circuits. 3DIC 2013: 1-5 - 2012
- [c3]Wei Guo, Geert Van der Plas, Andrej Ivankovic, Geert Eneman, Vladimir Cherman, Bart De Wachter, Abdelkarim Mercha, Mario Gonzalez, Yann Civale, Augusto Redolfi, Thibault Buisson, A. Jourdan, Bart Vandevelde, Kenneth J. Rebibis, Ingrid De Wolf, Antonio La Manna, Gerald Beyer, Eric Beyne
, Bart Swinnen:
3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps. ICICDT 2012: 1-4 - 2010
- [c2]Yann Civale, Marcel Gonzalez, Deniz Sabuncuoglu Tezcan, Youssef Travaly, Philippe Soussan, Eric Beyne
A novel concept for ultra-low capacitance via-last TSV. 3DIC 2010: 1-4
2000 – 2009
- 2009
- [c1]Yann Civale, Deniz Sabuncuoglu Tezcan, Harold G. G. Philipsen
Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping. 3DIC 2009: 1-4
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