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Jia-Jing Chen
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2020 – today
- 2020
- [j3]Xin Si
, Rui Liu
A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. IEEE J. Solid State Circuits 55(1): 189-202 (2020) - [j2]Yen-Cheng Chiu, Zhixiao Zhang, Jia-Jing Chen, Xin Si
A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors. IEEE J. Solid State Circuits 55(10): 2790-2801 (2020)
2010 – 2019
- 2019
- [j1]Xin Si
A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(11): 4172-4185 (2019) - [c5]Zhixiao Zhang, Jia-Jing Chen, Xin Si, Yung-Ning Tu, Jian-Wei Su
A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors. A-SSCC 2019: 217-218 - [c4]Xin Si
A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. ISSCC 2019: 396-398 - [c3]Ruiqi Guo
A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS. VLSI Circuits 2019: 120- - 2018
- [c2]Rui Liu, Xiaochen Peng, Xiaoyu Sun, Win-San Khwa, Xin Si
Parallelizing SRAM arrays with customized bit-cell for binary neural networks. DAC 2018: 21:1-21:6 - [c1]Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xin Si
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors. ISSCC 2018: 496-498
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