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Zhaopeng Wei

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2010 – 2019

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2019
[c4]
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Gilles Jacquemod, Zhaopeng Wei, Yves Leduc, Emeric de Foucauld, Jérôme Prouvée, B. Blampey:
New design of analog and mixed-signal cells using back-gate cross-coupled structure. VLSI-SoC 2019: 21-26
2017
[c3]
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Zhaopeng Wei, Yves Leduc, Emeric de Foucauld, Gilles Jacquemod:
Novel building blocks for PLL using complementary logic in 28nm UTBB-FDSOI technology. NEWCAS 2017: 121-124
2016
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Zhaopeng Wei, Gilles Jacquemod, Philippe Lorenzini, Frédéric Hameau, Emeric de Foucauld, Yves Leduc:
Study and Reduction of Variability in 28 nm Fully Depleted Silicon on Insulator Technology. J. Low Power Electron. 12(1): 64-73 (2016)
[c2]
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Gilles Jacquemod, Zhaopeng Wei, Yves Leduc, Cyril Jacquemod:
New QVCO design using UTBB FDSOI technology. EWME 2016: 1-4
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Zhaopeng Wei, Yves Leduc, Gilles Jacquemod, Emeric de Foucauld:
UTBB-FDSOI complementary logic for high quality analog signal processing. ICECS 2016: 572-575

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