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Shiva Kiran
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2020 – today
- 2023
- [j5]Ahmad Khairi, Yoel Krupnik
, Amir Laufer, Yoav Segal, Marco Cusmai, Itamar Levin
A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels. IEEE J. Solid State Circuits 58(1): 8-18 (2023) - [j4]Yuanming Zhu
A 38-GS/s 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET. IEEE J. Solid State Circuits 58(8): 2300-2313 (2023) - 2022
- [c9]Yuanming Zhu
A 38GS/s 7b Time-Interleaved Pipelined-SAR ADC with Speed-Enhanced Bootstrapped Switch in 22nm FinFET. CICC 2022: 1-2 - [c8]Yoav Segal, Amir Laufer, Ahmad Khairi, Yoel Krupnik, Marco Cusmai, Itamar Levin, Ari Gordon, Yaniv Saban, Vitali Rahinskj, Gadi Ori, Noam Familia, Stas Litski, Tali Warshavsky, Udi Virobnik, Yeshayahu Horwitz, Ajay Balankutty, Shiva Kiran, Samuel Palermo
A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation. ISSCC 2022: 114-116 - 2021
- [c7]Shiva Kiran, Ajay Balankutty, Yutao Liu, Rajeev Dokania, Hariprasath Venkataraman, Priya Wali
A 56GHz Receiver Analog Front End for 224Gb/s PAM-4 SerDes in 10nm CMOS. VLSI Circuits 2021: 1-2 - 2020
- [c6]Yuanming Zhu
A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS. CICC 2020: 1-4
2010 – 2019
- 2019
- [j3]Shiva Kiran
A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS. IEEE J. Solid State Circuits 54(3): 659-671 (2019) - [c5]Shiva Kiran, Shengchang Cai, Ying Luo, Sebastian Hoyos, Samuel Palermo:
A 32 Gb/s ADC-Based PAM-4 Receiver with 2-bit/Stage SAR ADC and Partially-Unrolled DFE. CICC 2019: 1-4 - [c4]Julian Camilo Gomez Diaz, Shiva Kiran, Samuel Palermo, Sebastian Hoyos:
Jitter-Robust Multicarrier ADC-Based Serial Link Receiver Architecture : (Invited Special Session Paper). MWSCAS 2019: 1151-1154 - 2018
- [c3]Shiva Kiran, Shengchang Cai, Ying Luo, Sebastian Hoyos, Samuel Palermo:
A 32 Gb/s ADC-based PAM-4 receiver with 2-bit/stage SAR ADC and partially-unrolled DFE. CICC 2018: 1-4 - 2017
- [j2]Shengchang Cai
A 25 GS/s 6b TI Two-Stage Multi-Bit Search ADC With Soft-Decision Selection Algorithm in 65 nm CMOS. IEEE J. Solid State Circuits 52(8): 2168-2179 (2017) - 2016
- [j1]Samuel Palermo, Sebastian Hoyos, Ayman Shafik, Ehsan Zhian Tabasy, Shengchang Cai, Shiva Kiran, Keytaek Lee:
CMOS ADC-based receivers for high-speed electrical and optical links. IEEE Commun. Mag. 54(10): 168-175 (2016) - 2015
- [c2]Shengchang Cai, Ehsan Zhian Tabasy, Ayman Shafik, Shiva Kiran, Sebastian Hoyos, Samuel Palermo:
A 25GS/s 6b TI binary search ADC with soft-decision selection in 65nm CMOS. VLSIC 2015: 158- - 2014
- [c1]Shiva Kiran, Sebastian Hoyos, Samuel Palermo:
A single parity check forward error correction method for high speed I/O. GlobalSIP 2014: 652-655
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