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Brian Dupaix
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2020 – today
- 2020
- [j6]Thomas Schultz
, Rashmi Jha
Vulnerabilities and Reliability of ReRAM Based PUFs and Memory Logic. IEEE Trans. Reliab. 69(2): 690-698 (2020)
2010 – 2019
- 2019
- [j5]Ramy Tantawy
Wide-Bandwidth, High-Linearity, 2.8-GS/s, 10-bit Accurate Sample and Hold Amplifier in 130-nm SiGe BiCMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(5): 1758-1768 (2019) - [j4]Roman Fragasse
Analysis of SRAM Enhancements Through Sense Amplifier Capacitive Offset Correction and Replica Self-Timing. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(6): 2037-2050 (2019) - [c9]Matthew J. Casto, Brian Dupaix, Pompei Len Orlando, Waleed Khalil:
Process Specific Functions for Assurance of Analog/Mixed-Signal Integrated Circuits. MWSCAS 2019: 456-459 - 2018
- [j3]Brandon Mathieu
A Capacitively Coupled, Pseudo Return-to-Zero Input, Latched-Bias Data Receiver. IEEE J. Solid State Circuits 53(9): 2500-2511 (2018) - [c8]Ramy Tantawy
A High Linearity, 2.8 GS/s, 10-bit Accurate, Sample and Hold Amplifier in 130 nm SiGe BiCMOS. ISCAS 2018: 1-4 - [c7]Moataz Abdelfattah, Muhammad Swilam, Brian Dupaix, Dale Shane Smith, Ayman A. Fayed
An on-chip resonant-gate-drive switched-capacitor converter for near-threshold computing achieving 70.2% efficiency at 0.92A/mm2 current density and 0.4V output. ISSCC 2018: 438-440 - [c6]Roman Fragasse
Sense amplifier offset cancellation and replica timing calibration for high-speed SRAMs. LASCAS 2018: 1-5 - 2017
- [j2]Lucas Duncan
A 10-bit DC-20-GHz Multiple-Return-to-Zero DAC With >48-dB SFDR. IEEE J. Solid State Circuits 52(12): 3262-3275 (2017) - [c5]Muhammad Swilam, Ahmed Naguib Mohamed
A calibration-free low-power supply-pushing reduction circuit (SPRC) for LC VCOs. ISCAS 2017: 1-4 - [c4]Lucas Duncan, Brian Dupaix, Jamin J. McCue, Brandon Mathieu, Matthew LaRue, Mesfin Teshome, Myung-Jun Choe, Waleed Khalil:
16.6 A 10b DC-to-20GHz multiple-return-to-zero DAC with >48dB SFDR. ISSCC 2017: 286-287 - 2016
- [j1]Jamin J. McCue, Brian Dupaix, Lucas Duncan, Brandon Mathieu, Samantha McDonnell, Vipul J. Patel
A Time-Interleaved Multimode ΔΣ RF-DAC for Direct Digital-to-RF Synthesis. IEEE J. Solid State Circuits 51(5): 1109-1124 (2016) - 2015
- [c3]Moataz Abdelfattah, Brian Dupaix, Syed R. Naqvi, Waleed Khalil:
A fully-integrated switched capacitor voltage regulator for near-threshold applications. ISCAS 2015: 201-204 - 2014
- [c2]Waleed Khalil, Jamin J. McCue, Brian Dupaix, Wagdy Gaber, Sami Smaili, Yehia Massoud:
On the design of RF-DACs for random acquisition based reconfigurable receivers. ISCAS 2014: 610-613 - [c1]Moataz Abdelfattah, Syed Roomi Naqvi, Brian Dupaix, Waleed Khalil:
Tracking energy efficiency of near-threshold design using process variation control techniques. NEWCAS 2014: 233-236
Coauthor Index
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