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Luka Daoud
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2020 – today
- 2022
- [j3]Luka Daoud
, Nader Rafla:
Efficient mitigation technique for Black Hole router attack in Network-on-Chip. Microprocess. Microsystems 94: 104658 (2022) - [c15]Luka Daoud, Nader Rafla:
Energy-Efficient Black Hole Router Detection in Network-on-Chip. SOCC 2022: 1-6 - 2020
- [j2]Luka Daoud, Muhammad Kamran Latif, H. S. Jacinto, Nader Rafla:
A fully pipelined FPGA accelerator for scale invariant feature transform keypoint descriptor matching. Microprocess. Microsystems 72 (2020) - [j1]Fady Hussein, Luka Daoud, Nader Rafla:
A reconfigurable HexCell-based systolic array architecture for evolvable hardware on FPGA. Microprocess. Microsystems 74: 103014 (2020) - [i1]Luka Daoud, Muhammad Kamran Latif, H. S. Jacinto, Nader Rafla:
A fully pipelined FPGA accelerator for scale invariant feature transform keypoint descriptor matching, . CoRR abs/2012.09666 (2020)
2010 – 2019
- 2019
- [c14]Luka Daoud, Fady Hussein, Nader Rafla:
Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS). CATA 2019: 36-44 - [c13]Luka Daoud, Nader Rafla:
Analysis of Black Hole Router Attack in Network-on-Chip. MWSCAS 2019: 69-72 - [c12]Luka Daoud, Nader Rafla:
Detection and prevention protocol for black hole attack in network-on-chip. NOCS 2019: 22:1-22:2 - [c11]Luka Daoud, Nader Rafla:
Runtime Packet-Dropping Detection of Faulty Nodes in Network-on-Chip. SoCC 2019: 266-271 - 2018
- [c10]Fady Hussein, Luka Daoud, Nader Rafla:
HexCell: a Hexagonal Cell for Evolvable Systolic Arrays on FPGAs: (Abstract Only). FPGA 2018: 293 - [c9]Luka Daoud, Muhammad Kamran Latif, Nader Rafla:
SIFT Keypoint Descriptor Matching Algorithm: A Fully Pipelined Accelerator on FPGA(Abstract Only). FPGA 2018: 294 - [c8]Luka Daoud:
Secure Network-on-Chip Architectures for MPSoC: Overview and Challenges. MWSCAS 2018: 542-543 - [c7]Luka Daoud, Nader Rafla:
Routing Aware and Runtime Detection for Infected Network-on-Chip Routers. MWSCAS 2018: 775-778 - [c6]Muhammad Kamran Latif, H. S. Jacinto, Luka Daoud, Nader Rafla:
Optimization of a Quantum-Secure Sponge-Based Hash Message Authentication Protocol. MWSCAS 2018: 984-987 - [c5]Luka Daoud, Fady Hussein, Nader Rafla:
Real-time Bitstream Decompression Scheme for FPGAs Reconfiguration. MWSCAS 2018: 1082-1085 - 2017
- [c4]H. S. Jacinto, Luka Daoud, Nader Rafla:
High level synthesis using vivado HLS for optimizations of SHA-3. MWSCAS 2017: 563-566 - 2016
- [c3]Danyal Mohammadi, Luka Daoud, Nader Rafla, Said Ahmed-Zaid:
Zynq-based SoC implementation of an induction machine control algorithm. MWSCAS 2016: 1-4 - 2014
- [c2]Luka Daoud, Dawid Zydek, Henry Selvaraj:
A Survey on Design and Implementation of Floating Point Adder in FPGA. ICSEng 2014: 885-892 - 2013
- [c1]Luka Daoud, Dawid Zydek, Henry Selvaraj:
A Survey of High Level Synthesis Languages, Tools, and Compilers for Reconfigurable High Performance Computing. ICSS 2013: 483-492
Coauthor Index
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