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Vianney Lapotre
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2020 – today
- 2024
- [c34]Moritz Peters
, Nicolas Gaudin
On The Effect of Replacement Policies on The Security of Randomized Cache Architectures. AsiaCCS 2024 - [c33]Hongwei Zhao, Vianney Lapôtre, Guy Gogniat:
Communication Architecture Under Siege: An In-depth Analysis of Fault Attack Vulnerabilities and Countermeasures. CSR 2024: 890-896 - [c32]Nicolas Gaudin, Pascal Cotret, Guy Gogniat, Vianney Lapôtre:
A Fine-Grained Dynamic Partitioning Against Cache-Based Timing Attacks via Cache Locking. ISVLSI 2024: 173-179 - [c31]William Pensec, Francesco Regazzoni Alari, Vianney Lapotre, Guy Gogniat:
Defending the Citadel: Fault Injection Attacks Against Dynamic Information Flow Tracking and Related Countermeasures. ISVLSI 2024: 180-185 - 2023
- [b1]Vianney Lapotre:
Contributions à la sécurité des systèmes embarqués face aux attaques logiques et physiques. (Contributions to the security of embedded systems against logical and physical attacks). University of Southern Brittany, Vannes, Morbihan, France, 2023 - [c30]Nicolas Gaudin, Jean-Loup Hatchikian-Houdot, Frédéric Besson, Pascal Cotret, Guy Gogniat, Guillaume Hiet, Vianney Lapotre, Pierre Wilke:
Work in Progress: Thwarting Timing Attacks in Microcontrollers using Fine-grained Hardware Protections. EuroS&P Workshops 2023: 304-310 - [i4]Moritz Peters
On The Effect of Replacement Policies on The Security of Randomized Cache Architectures. CoRR abs/2312.06235 (2023) - 2022
- [j12]Maria Mushtaq
The Kingsguard OS-level mitigation against cache side-channel attacks using runtime detection. Ann. des Télécommunications 77(11-12): 731-747 (2022) - [c29]Noura Ait Manssour, Vianney Lapôtre, Guy Gogniat
Processor Extensions for Hardware Instruction Replay against Fault Injection Attacks. DDECS 2022: 26-31 - 2020
- [j11]Ayaz Akram
Meet the Sherlock Holmes' of Side Channel Leakage: A Survey of Cache SCA Detection Techniques. IEEE Access 8: 70836-70860 (2020) - [j10]Maria Mushtaq
WHISPER: A Tool for Run-Time Detection of Side-Channel Attacks. IEEE Access 8: 83871-83900 (2020) - [j9]Maria Mushtaq
Winter is here! A decade of cache-based side-channel attacks, detection & mitigation for RSA. Inf. Syst. 92: 101524 (2020) - [j8]Cyrielle Feron, Loïc Lagadec, Vianney Lapôtre:
Automated exploration of homomorphic encryption scheme input parameters. J. Inf. Secur. Appl. 55: 102627 (2020) - [j7]Muhammad Asim Mukhtar, Maria Mushtaq
FLUSH + PREFETCH: A countermeasure against access-driven cache-based side-channel attacks. J. Syst. Archit. 104: 101698 (2020) - [c28]Ghita Harcha, Vianney Lapôtre, Cyrille Chavet, Philippe Coussy:
Toward Secured IoT Devices: A Shuffled 8-Bit AES Hardware Implementation. ISCAS 2020: 1-4
2010 – 2019
- 2019
- [c27]Maria Mushtaq, Ayaz Akram, Muhammad Khurram Bhatti, Usman Ali, Vianney Lapotre, Guy Gogniat
Sherlock Holmes of Cache Side-Channel Attacks in Intel's x86 Architecture. CNS 2019: 64-72 - 2018
- [j6]Vincent Migliore
Hardware/Software Co-Design of an Accelerator for FV Homomorphic Encryption Scheme Using Karatsuba Algorithm. IEEE Trans. Computers 67(3): 335-347 (2018) - [j5]Maria Mendez Real
Application Deployment Strategies for Spatial Isolation on Many-Core Accelerators. ACM Trans. Embed. Comput. Syst. 17(2): 55:1-55:31 (2018) - [c26]Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre
A novel lightweight hardware-assisted static instrumentation approach for ARM SoC using debug components. AsianHOST 2018: 92-97 - [c25]Maria Mushtaq, Ayaz Akram, Muhammad Khurram Bhatti, Rao Naveed Bin Rais
Run-time Detection of Prime + Probe Side-Channel Attack on AES Encryption Algorithm. GIIS 2018: 1-5 - [c24]Maria Mushtaq, Ayaz Akram, Muhammad Khurram Bhatti, Maham Chaudhry, Muhammad Muneeb Yousaf, Umer Farooq, Vianney Lapotre, Guy Gogniat
Machine Learning For Security: The Case of Side-Channel Attack Detection at Run-time. ICECS 2018: 485-488 - [c23]Maria Mushtaq
NIGHTs-WATCH: a cache-based side-channel intrusion detector using hardware performance counters. HASP@ISCA 2018: 1:1-1:8 - [c22]Cyrielle Feron, Vianney Lapotre
Fast Evaluation of Homomorphic Encryption Schemes Based on Ring-LWE. NTMS 2018: 1-5 - [c21]Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Arnab Kumar Biswas
A small and adaptive coprocessor for information flow tracking in ARM SoCs. ReConFig 2018: 1-8 - [i3]Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, Guy Gogniat:
Towards a hardware-assisted information flow tracking ecosystem for ARM processors. CoRR abs/1811.05465 (2018) - [i2]Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Arnab Kumar Biswas, Vianney Lapôtre, Guy Gogniat:
A small and adaptive coprocessor for information flow tracking in ARM SoCs. CoRR abs/1812.01541 (2018) - [i1]Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Arnab Kumar Biswas, Vianney Lapôtre, Guy Gogniat:
A novel lightweight hardware-assisted static instrumentation approach for ARM SoC using debug components. CoRR abs/1812.01667 (2018) - 2017
- [j4]Vianney Lapotre
Dynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decoding. EURASIP J. Adv. Signal Process. 2017: 35 (2017) - [j3]Vincent Migliore, Cédric Seguin, Maria Mendez Real
A High-Speed Accelerator for Homomorphic Encryption using the Karatsuba Algorithm. ACM Trans. Embed. Comput. Syst. 16(5s): 138:1-138:17 (2017) - [c20]Guillaume Bonnoron, Caroline Fontaine, Guy Gogniat
Somewhat/Fully Homomorphic Encryption: Implementation Progresses and Challenges. C2SI 2017: 68-82 - [c19]Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, Guy Gogniat
ARMHEx: A hardware extension for DIFT on ARM-based SoCs. FPL 2017: 1-7 - [c18]Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, Guy Gogniat
ARMHEx: A framework for efficient DIFT in real-world SoCs. FPL 2017: 1 - [c17]Cyrielle Feron, Vianney Lapotre, Loïc Lagadec:
PAnTHErS: A Prototyping and Analysis Tool for Homomorphic Encryption Schemes. SECRYPT 2017: 359-366 - 2016
- [j2]Vianney Lapotre
A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 383-387 (2016) - [c16]Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, Guy Gogniat
Towards a hardware-assisted information flow tracking ecosystem for ARM processors. FPL 2016: 1-2 - [c15]Vincent Migliore, Maria Mendez Real, Vianney Lapotre, Arnaud Tisserand, Caroline Fontaine, Guy Gogniat
Fast polynomial arithmetic for Somewhat Homomorphic Encryption operations in hardware with Karatsuba algorithm. FPT 2016: 209-212 - [c14]Maria Mendez Real, Vincent Migliore, Vianney Lapotre, Guy Gogniat
ALMOS Many-Core Operating System Extension with New Secure-Enable Mechanisms for Dynamic Creation of Secure Zones. PDP 2016: 820-824 - [c13]Maria Mendez Real, Philipp Wehner, Vincent Migliore, Vianney Lapotre, Diana Göhringer, Guy Gogniat
Dynamic spatially isolated secure zones for NoC-based many-core accelerators. ReCoSoC 2016: 1-6 - [c12]Maria Mendez Real, Philipp Wehner, Jens Rettkowski, Vincent Migliore, Vianney Lapotre, Diana Göhringer
MPSoCSim extension: An OVP simulator for the evaluation of cluster-based multi and many-core architectures. SAMOS 2016: 342-347 - 2015
- [c11]Anastasiia Butko, Rafael Garibotti
A trace-driven approach for fast and accurate simulation of manycore architectures. ASP-DAC 2015: 707-712 - [c10]Charles Effiong, Vianney Lapotre
On the Performance Exploration of 3D NoCs with Resistive-Open TSVs. ISVLSI 2015: 579-584 - [c9]Vincent Migliore, Maria Mendez Real, Vianney Lapotre, Arnaud Tisserand, Caroline Fontaine, Guy Gogniat
Exploration of polynomial multiplication algorithms for homomorphic encryption schemes. ReConFig 2015: 1-6 - 2014
- [c8]Anelise Kologeski, Fernanda Lima Kastensmidt
Performance exploration of partially connected 3D NoCs under manufacturing variability. NEWCAS 2014: 61-64 - 2013
- [j1]Vianney Lapotre, Philippe Coussy, Cyrille Chavet:
Introduction de la prédiction de branchement dans la synthèse de haut niveau. Tech. Sci. Informatiques 32(2): 281-301 (2013) - [c7]Vianney Lapotre
Stopping-Free Dynamic Configuration of a Multi-ASIP Turbo Decoder. DSD 2013: 155-162 - [c6]Vianney Lapotre, Philippe Coussy, Cyrille Chavet, Hugues Wouafo, Robin Danilo:
Dynamic branch prediction for high-level synthesis. FPL 2013: 1-6 - [c5]Vianney Lapotre
Optimizations for an efficient reconfiguration of an ASIP-based turbo decoder. ISCAS 2013: 493-496 - [c4]Vianney Lapotre, Purushotham Murugappa, Guy Gogniat
A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context. ISVLSI 2013: 40-45 - [c3]Vianney Lapotre
An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture. ReCoSoC 2013: 1-8 - [c2]Purushotham Murugappa, Vianney Lapotre, Amer Baghdadi
Rapid design and prototyping of a reconfigurable decoder architecture for QC-LDPC codes. RSP 2013: 87-93 - 2012
- [c1]Vianney Lapotre, Guy Gogniat
An analytical approach for sizing of heterogeneous multiprocessor flexible platforms for iterative demapping and channel decoding. ReConFig 2012: 1-6
Coauthor Index
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last updated on 2024-10-07 21:18 CEST by the dblp team
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