default search action
Manish Kumar Jaiswal
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2010 – 2019
- 2019
- [j13]Manish Kumar Jaiswal
, Hayden Kwok-Hay So
PACoGen: A Hardware Posit Arithmetic Core Generator. IEEE Access 7: 74586-74601 (2019) - [j12]Manish Kumar Jaiswal
Design of quadruple precision multiplier architectures with SIMD single and double precision support. Integr. 65: 163-174 (2019) - 2018
- [j11]Manish Kumar Jaiswal
An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division. Circuits Syst. Signal Process. 37(1): 383-407 (2018) - [j10]Farkhanda Syed
Fast Content Updating Algorithm for an SRAM-Based TCAM on FPGA. IEEE Embed. Syst. Lett. 10(3): 73-76 (2018) - [c17]Manish Kumar Jaiswal, Hayden Kwok-Hay So
Universal number posit arithmetic generator on FPGA. DATE 2018: 1159-1162 - [c16]Manish Kumar Jaiswal, Hayden Kwok-Hay So
Architecture Generator for Type-3 Unum Posit Adder/Subtractor. ISCAS 2018: 1-5 - 2017
- [j9]Manish Kumar Jaiswal
Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(2): 386-398 (2017) - 2016
- [c15]Manish Kumar Jaiswal, Hayden Kwok-Hay So
Architecture for quadruple precision floating point division with multi-precision support. ASAP 2016: 239-240 - [c14]Maolin Wang, Ho-Cheung Ng, Bob M. F. Chung, B. Sharat Chandra Varma, Manish Kumar Jaiswal, Kevin K. Tsia
Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA. FPT 2016: 261-264 - [c13]Manish Kumar Jaiswal, Hayden Kwok-Hay So
Taylor Series Based Architecture for Quadruple Precision Floating Point Division. ISVLSI 2016: 518-523 - [c12]Manish Kumar Jaiswal, Hayden Kwok-Hay So
Dual-mode double precision division architecture. MWSCAS 2016: 1-4 - [c11]Ho-Cheung Ng, Maolin Wang, Bob M. F. Chung, B. Sharat Chandra Varma
High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform. ReConFig 2016: 1-6 - 2015
- [j8]Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So
Configurable Architectures for Multi-Mode Floating Point Adders. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2079-2090 (2015) - [j7]Zahid Ullah, Manish Kumar Jaiswal, Ray C. C. Cheung
Z-TCAM: An SRAM-based Architecture for TCAM. IEEE Trans. Very Large Scale Integr. Syst. 23(2): 402-406 (2015) - [c10]Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So
Architecture for Dual-Mode Quadruple Precision Floating Point Adder. ISVLSI 2015: 249-254 - [c9]Manish Kumar Jaiswal, Hayden Kwok-Hay So
Dual-mode double precision / two-parallel single precision floating point multiplier architecture. VLSI-SoC 2015: 213-218 - 2014
- [j6]Zahid Ullah, Manish Kumar Jaiswal, Ray C. C. Cheung
E-TCAM: An Efficient SRAM-Based Architecture for TCAM. Circuits Syst. Signal Process. 33(10): 3123-3144 (2014) - [j5]Manish Kumar Jaiswal, Ray C. C. Cheung
Series Expansion based Efficient Architectures for Double Precision Floating Point Division. Circuits Syst. Signal Process. 33(11): 3499-3526 (2014) - [j4]Manish Kumar Jaiswal, Ray C. C. Cheung
Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder. IEEE Trans. Circuits Syst. II Express Briefs 61-II(7): 521-525 (2014) - [c8]Manish Kumar Jaiswal, Ray C. C. Cheung
Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division. ISVLSI 2014: 332-337 - 2013
- [j3]Manish Kumar Jaiswal, Ray C. C. Cheung
VLSI Implementation of Double-Precision Floating-Point Multiplier Using Karatsuba Technique. Circuits Syst. Signal Process. 32(1): 15-27 (2013) - [j2]Manish Kumar Jaiswal, Ray C. C. Cheung
Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support. Microelectron. J. 44(5): 421-430 (2013) - [c7]Zahid Ullah, Manish Kumar Jaiswal, Ray C. C. Cheung
Design space explorations of Hybrid-Partitioned TCAM (HP-TCAM). FPL 2013: 1-4 - 2012
- [j1]Manish Kumar Jaiswal, Nitin Chandrachoodan
FPGA-Based High-Performance and Scalable Block LU Decomposition Architecture. IEEE Trans. Computers 61(1): 60-72 (2012) - [c6]Manish Kumar Jaiswal, Ray C. C. Cheung
High Performance Reconfigurable Architecture for Double Precision Floating Point Division. ARC 2012: 302-313 - [c5]Manish Kumar Jaiswal, Ray C. C. Cheung
Area-Efficient Architectures for Large Integer and Quadruple Precision Floating Point Multipliers. FCCM 2012: 25-28 - [c4]Manish Kumar Jaiswal, Ray C. C. Cheung
Area-Efficient FPGA Implementation of Quadruple Precision Floating Point Multiplier. IPDPS Workshops 2012: 376-382 - [c3]Zahid Ullah, Manish Kumar Jaiswal, Y. C. Chan, Ray C. C. Cheung
FPGA Implementation of SRAM-based Ternary Content Addressable Memory. IPDPS Workshops 2012: 383-389
2000 – 2009
- 2009
- [c2]Manish Kumar Jaiswal, Nitin Chandrachoodan
Efficient Implementation of Floating-Point Reciprocator on FPGA. VLSI Design 2009: 267-271 - 2008
- [c1]Manish Kumar Jaiswal, Nitin Chandrachoodan
Efficient Implementation of IEEE Double Precision Floating-Point Multiplier on FPGA. ICIIS 2008: 1-4
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-07 21:25 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: