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Hiroe Iwasaki
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2020 – today
- 2024
- [c17]Kento Mishima, Naoya Niwa
, Kazutoshi Wakabayashi, Hiroe Iwasaki:
ISP Parameter Optimization and FPGA Implementation for Object Detection in Low-Light Conditions. COOL CHIPS 2024: 1-3 - 2023
- [j12]Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta
An Efficient Reference Image Sharing Method for the Image-Division Parallel Video Encoding Architecture. IEICE Trans. Electron. 106(6): 312-320 (2023) - [j11]Daisuke Kobayashi, Ken Nakamura, Masaki Kitahara, Tatsuya Osawa, Yuya Omori, Takayuki Onishi, Hiroe Iwasaki
A Low-Latency 4K HEVC Multi-Channel Encoding System with Content-Aware Bitrate Control for Live Streaming. IEICE Trans. Inf. Syst. 106(1): 46-57 (2023) - 2022
- [c16]Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta
An Efficient Reference Image Sharing Method for the Parallel Video Encoding Architecture. COOL CHIPS 2022: 1-3 - [c15]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Hiroe Iwasaki
OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization. MWSCAS 2022: 1-4 - [c14]Masayuki Sato
A Partitioned Memory Architecture with Prefetching for Efficient Video Encoders. PDCAT 2022: 288-300 - 2020
- [j10]Ken Nakamura, Daisuke Kobayashi, Yuya Omori, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. IEICE Trans. Electron. 103-C(3): 77-84 (2020)
2010 – 2019
- 2019
- [c13]Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. COOL CHIPS 2019: 1-3 - [c12]Daisuke Kobayashi, Ken Nakamura, Tatsuya Osawa, Yuya Omori, Takayuki Onishi, Hiroe Iwasaki
A Real-Time 4K HEVC Multi-Channel Encoding System with Content-Aware Bitrate Control. GLOBECOM 2019: 1-6 - [c11]Yuya Omori, Ken Nakamura, Takayuki Onishi, Daisuke Kobayashi, Tatsuya Osawa, Hiroe Iwasaki
4K 120fps HEVC Temporal Scalable Encoder with Super Low Delay. ICECS 2019: 410-413 - [c10]Takayuki Onishi, Yuya Omori, Ken Nakamura, Hiroe Iwasaki
A Low Power Motion Estimation Engine with Adaptive Bit-Shifted SAD Calculation. ISCAS 2019: 1-5 - 2018
- [j9]Daisuke Kobayashi
A 4K/60p HEVC Real-Time Encoding System With High Quality HDR Color Representations. IEEE Trans. Consumer Electron. 64(4): 433-441 (2018) - [j8]Yuya Omori
A 120 fps High Frame Rate Real-time HEVC Video Encoder with Parallel Configuration Scalable to 4K. IEEE Trans. Multi Scale Comput. Syst. 4(4): 491-499 (2018) - [j7]Takayuki Onishi
A Single-Chip 4K 60-fps 4: 2: 2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1930-1938 (2018) - [c9]Daisuke Kobayashi, Ken Nakamura, Takayuki Onishi, Yasuyuki Nakajima, Hiroe Iwasaki
An HEVC real-time encoding system with high quality HDR color representations. ICCE 2018: 1-2 - 2017
- [c8]Yuya Omori, Takayuki Onishi, Hiroe Iwasaki
A 120 fps high frame rate real-time HEVC video encoder with parallel configuration scalable to 4K. COOL Chips 2017: 1-3 - 2015
- [c7]Hiroe Iwasaki
Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure. Hot Chips Symposium 2015: 1-24 - [c6]Takayuki Onishi, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Jia Su, Ken Nakamura, Koyo Nitta
Single-chip 4K 60fps 4: 2: 2 HEVC video encoder LSI with 8K scalability. VLSIC 2015: 54- - 2012
- [j6]Koyo Nitta
An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures. IEICE Trans. Electron. 95-C(4): 432-440 (2012) - [c5]Mitsuo Ikeda, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Hiroe Iwasaki
MVC real-time video encoder for full-HDTV 3D video. ICCE 2012: 166-167
2000 – 2009
- 2007
- [j5]Hiroe Iwasaki
Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level. IEEE Trans. Very Large Scale Integr. Syst. 15(9): 1055-1059 (2007) - 2005
- [j4]Hiroe Iwasaki
MPEG-2 real-time software CODEC for full-duplex transmission application over IP networks. Syst. Comput. Jpn. 36(2): 33-41 (2005) - [j3]Minoru Inamori, Hiroe Iwasaki
New set-top box for interactive visual communication of home entertainment using MPEG-2 full-duplex CODEC LSI. IEEE Trans. Consumer Electron. 51(2): 640-641 (2005) - 2003
- [c4]Hiroe Iwasaki, Jiro Naganuma, Yasuyuki Nakajima, Yutaka Tashiro, Ken Nakamura, Takeshi Yoshitome, Takayuki Onishi, Mitsuo Ikeda, Takaaki Izuoka, Makoto Endo:
A 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems. CICC 2003: 177-180 - [c3]Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Makoto Endo:
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level. DATE 2003: 20002-20007 - 2002
- [j2]Hiroe Iwasaki
Advanced concurrent design environment for multimedia system LSIs. Syst. Comput. Jpn. 33(14): 72-80 (2002)
1990 – 1999
- 1999
- [j1]Mitsuo Ikeda, Toshio Kondo, Koyo Nitta
SuperENC: MPEG-2 video encoder chip. IEEE Micro 19(4): 56-65 (1999) - [c2]Katsuyuki Ochiai, Hiroe Iwasaki
High-speed Software-based Platform for Embedded Software of a Single-chip MPEG-2 Video Encoder LSI with HDTV Scalabilit. DATE 1999: 303-308 - [c1]Hiroe Iwasaki
On-Chip Multimedia Real-Time OS and its MPEG-2 Applications. RTCSA 1999: 200-203
Coauthor Index
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