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Michel Haond
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2010 – 2019
- 2019
- [c8]Lucas Nyssens, Arka Halder
, Babak Kazemi Esfeh, Nicolas Planes, Michel Haond, Denis Flandre, Jean-Pierre Raskin, Valeriya Kilchytska
Self-Heating in 28 FDSOI UTBB MOSFETs at Cryogenic Temperatures. ESSDERC 2019: 162-165 - 2017
- [c7]B. Kazemi Esfeh, Valeria Kilchytska
Back-gate bias effect on UTBB-FDSOI non-linearity performance. ESSDERC 2017: 148-151 - 2016
- [c6]R. Berthelon, François Andrieu, P. Perreau, E. Baylac, A. Pofelski, Emmanuel Josse, Didier Dutartre, A. Claverie, Michel Haond:
Performance and layout effects of SiGe channel in 14nm UTBB FDSOI: SiGe-first vs. SiGe-last integration. ESSDERC 2016: 127-130 - 2015
- [c5]Carlos Suarez-Segovia, Charles Leroux, Florian Domengie, Karen Dabertrand, Vincent Joseph, Giovanni Romano, Pierre Caubet, Stephane Zoll, Olivier Weber, Gérard Ghibaudo
Effective work function engineering by sacrificial lanthanum diffusion on HfON-based 14 nm NFET devices. ESSDERC 2015: 246-249 - [c4]Olivier Weber, Emmanuel Josse, J. Mazurier, Michel Haond:
Static and dynamic power management in 14nm FDSOI technology. ICICDT 2015: 1-4 - 2014
- [c3]François Andrieu, Mikaël Cassé, E. Baylac, P. Perreau, O. Nier, Denis Rideau, R. Berthelon, Franck Pourchon, A. Pofelski, Barbara De Salvo, C. Gallon, Vincent Mazzocchi, D. Barge, C. Gaumer, O. Gourhant, A. Cros, Vincent Barral, Rossella Ranica, Nicolas Planes, Walter Schwarzenbach, E. Richard, Emmanuel Josse, Olivier Weber, Franck Arnaud, Maud Vinet, Olivier Faynot
Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs. ESSDERC 2014: 106-109 - [c2]Sergej Makovejev, Babak Kazemi Esfeh, Jean-Pierre Raskin, Valeria Kilchytska
Variability of UTBB MOSFET analog figures of merit in wide frequency range. ESSDERC 2014: 222-225
2000 – 2009
- 2002
- [c1]Thierry Devoivre, M. Lunenborg, C. Julien, J.-P. Carrere, P. Ferreira, W. J. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger, P. Vannier, Y. Trouiller, Y. Rody, P.-J. Goirand, R. Palla, I. Thomas, F. Guyader, David Roy, B. Borot, Nicolas Planes, Sylvie Naudet, F. Pico, D. Duca, F. Lalanne, D. Heslinga, M. Haond:
Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC). MTDT 2002: 157-162
1990 – 1999
- 1999
- [j1]Michel Haond, Marie-Thérèse Basso, Walter deCoster, Jos Guelen, Christophe Lair:
Developing a 0.18-micron CMOS process. IEEE Micro 19(5): 16-22 (1999)
Coauthor Index
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