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Takashi Yokota
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2020 – today
- 2024
- [c62]Takeshi Ohkawa, Kenta Arai, Kanemitsu Ootsu, Takashi Yokota:
Alchemist: A Component-Oriented Development Tool of FPGA based on Publish/Subscribe Model. ICCE 2024: 1-6 - 2023
- [j19]Takashi Yokota, Kanemitsu Ootsu, Shun Kojima:
Enhancing Cup-Stacking Method for Collective Communication. IEICE Trans. Inf. Syst. 106(11): 1808-1821 (2023) - 2022
- [j18]Takashi Yokota, Kanemitsu Ootsu, Shun Kojima:
On a Cup-Stacking Concept in Repetitive Collective Communication. IEICE Trans. Inf. Syst. 105-D(7): 1325-1329 (2022) - [c61]Tatsuya Tsuchiya, Kanemitsu Ootsu, Takashi Yokota, Shun Kojima:
Assembly code translation from ARM64 to RISC-V. SNPD-Summer 2022: 68-73 - [c60]Jintaro Nogae, Kanemitsu Ootsu, Takashi Yokota, Shun Kojima:
Comparison of reinforcement learning in game AI. SNPD-Summer 2022: 82-86 - [c59]Shun Kojima, Yi Feng, Kazuki Maruta, Kanemitsu Ootsu, Takashi Yokota, Chang-Jun Ahn, Vahid Tarokh:
Towards Deep Learning-Guided Multiuser SNR and Doppler Shift Detection for Next-Generation Wireless Systems. VTC Spring 2022: 1-6 - 2021
- [c58]Yoshiki Kimura, Kanemitsu Ootsu, Tatsuya Tsuchiya, Takashi Yokota:
Development of RISC-V Based Soft-core Processor with Scalable Vector Extension for Embedded System. ACIT 2021: 13-18 - [c57]Shun Kojima, Yi Feng, Kazuki Maruta
, Kanemitsu Ootsu, Takashi Yokota, Chang-Jun Ahn, Vahid Tarokh:
Investigation of Input Signal Representation to CNN for Improving SNR Classification Accuracy. VTC Fall 2021: 1-5 - 2020
- [j17]Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa:
Genetic Node-Mapping Methods for Rapid Collective Communications. IEICE Trans. Inf. Syst. 103-D(1): 111-129 (2020) - [c56]Takashi Yokota, Kazunori Kojima, Shi-wook Lee, Yoshiaki Itoh:
Reduction of Speech Data Posteriorgrams by Compressing Maximum-likelihood State Sequences in Query by Example. APSIPA 2020: 649-653 - [c55]Tomoya Kikuchi, Yoshiki Kimura, Kanemitsu Ootsu, Takashi Yokota:
Development of Soft-Core Processor with Efficient Array Data Transfer Mechanism. CANDAR (Workshops) 2020: 411-415
2010 – 2019
- 2019
- [j16]Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa:
Accelerating Large-Scale Interconnection Network Simulation by Cellular Automata Concept. IEICE Trans. Inf. Syst. 102-D(1): 52-74 (2019) - [j15]Takeshi Ohkawa, Kazushi Yamashina, Takuya Matsumoto, Kanemitsu Ootsu, Takashi Yokota:
Automatic Generation Tool of FPGA Components for Robots. IEICE Trans. Inf. Syst. 102-D(5): 1012-1019 (2019) - [j14]Takanobu Baba, Shinpei Watanabe, Boaz Jessie Jackin
Fast Computation with Efficient Object Data Distribution for Large-Scale Hologram Generation on a Multi-GPU Cluster. IEICE Trans. Inf. Syst. 102-D(7): 1310-1320 (2019) - [c54]Masahiro Nissato, Hiroki Sugiyama, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota:
Realization and Preliminary Evaluation of MPI Runtime Environment on Android Cluster. AINA 2019: 407-418 - [c53]Yoshiki Kimura, Tomoya Kikuchi, Kanemitsu Ootsu, Takashi Yokota:
Proposal of Scalable Vector Extension for Embedded RISC-V Soft-Core Processor. CANDAR Workshops 2019: 435-439 - [c52]Takeshi Ohkawa, Yuhei Sugata, Harumi Watanabe, Nobuhiko Ogura, Kanemitsu Ootsu, Takashi Yokota:
High level synthesis of ROS protocol interpretation and communication circuit for FPGA. RoSE@ICSE 2019: 33-36 - [c51]Kengo Jingu, Kohta Shigenobu, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota:
Directive-Based Parallelization of For-Loops at LLVM IR Level. SNPD 2019: 421-426 - 2018
- [j13]Takeshi Ohkawa, Kazushi Yamashina, Hitomi Kimura, Kanemitsu Ootsu, Takashi Yokota:
FPGA Components for Integrating FPGAs into Robot Systems. IEICE Trans. Inf. Syst. 101-D(2): 363-375 (2018) - [j12]Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa:
A Genetic Approach for Accelerating Communication Performance by Node Mapping. IEICE Trans. Inf. Syst. 101-D(12): 2971-2975 (2018) - [c50]Hiromichi Wakatsuki, Takao Kido, Kenta Arai, Yuhei Sugata, Kanemitsu Ootsu, Takashi Yokota, Takeshi Ohkawa:
Development of a Robot Car by Single Line Search Method for White Line Detection with FPGA. FPT 2018: 415-418 - [c49]Kengo Jingu, Kohta Shigenobu, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota:
An Implementation of LLVM Pass for Loop Parallelization Based on IR-Level Directives. CANDAR Workshops 2018: 501-505 - [c48]Yuichi Nonaka, Daisuke Yoshida, Shogo Kitamura, Takashi Yokota, Madoka Hasegawa, Kanemitsu Ootsu:
Monocular color-IR imaging system applicable for various light environments. ICCE 2018: 1-5 - [c47]Takanobu Baba, Shinpei Watanabe, Boaz Jessie Jackin
Data Distribution Method for Fast Giga-scale Hologram Generation on a Multi-GPU Cluster. ApPLIED@PODC 2018: 37-40 - [c46]Takanobu Baba, Shinpei Watanabe, Boaz Jessie Jackin
Overcoming the difficulty of large-scale CGH generation on multi-GPU cluster. GPGPU@PPoPP 2018: 13-21 - 2017
- [j11]Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa:
A Static Packet Scheduling Approach for Fast Collective Communication by Using PSO. IEICE Trans. Inf. Syst. 100-D(12): 2781-2795 (2017) - [j10]Yuki Sawada
Performance of Android Cluster System Allowing Dynamic Node Reconfiguration. Wirel. Pers. Commun. 93(4): 1067-1087 (2017) - [c45]Yuhei Sugata, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota:
Acceleration of Publish/Subscribe Messaging in ROS-compliant FPGA Component. HEART 2017: 13:1-13:6 - [c44]Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa:
Large-Scale Interconnection Network Simulation Methods Based on Cellular Automata. CANDAR 2017: 58-67 - [c43]Kohta Shigenobu, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota:
A Translation Method of ARM Machine Code to LLVM-IR for Binary Code Parallelization and Optimization. CANDAR 2017: 575-579 - [c42]Shinpei Watanabe, Boaz Jessie Jackin
Acceleration of Large-Scale CGH Generation Using Multi-GPU Cluster. CANDAR 2017: 589-593 - [c41]Yuichi Nonaka, Daisuke Yoshida, Takashi Yokota, Madoka Hasegawa, Kanemitsu Ootsu:
Image Denoising Based on Human Visual Characteristics. ICAIP 2017: 78-84 - [c40]Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota, Katsuya Kikuchi, Masahiro Aoyagi:
Designing Efficient Parallel Processing in 3D Standard-Chip Stacking System with Standard Bus. MCSoC 2017: 128-135 - 2016
- [j9]Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa:
Enhancing Entropy Throttling: New Classes of Injection Control in Interconnection Networks. IEICE Trans. Inf. Syst. 99-D(12): 2911-2922 (2016) - [c39]Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa:
Introducing PSO for Optimal Packet Scheduling of Collective Communication. CANDAR 2016: 429-435 - [c38]Kazushi Yamashina, Hitomi Kimura, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota:
cReComp: Automated Design Tool for ROS-Compliant FPGA Component. MCSoC 2016: 138-145 - [c37]Takeshi Ohkawa, Kazushi Yamashina, Takuya Matsumoto, Kanemitsu Ootsu, Takashi Yokota:
Architecture exploration of intelligent robot system using ros-compliant FPGA component. RSP 2016: 72-78 - 2015
- [j8]Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa:
Relaxing Heavy Congestion by State Propagation. J. Inf. Process. 23(5): 730-743 (2015) - [c36]Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa:
Entropy Throttling: Towards Global Congestion Control of Interconnection Networks. CANDAR 2015: 40-49 - [c35]Yuki Suzuki, Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa:
Performance Improvement of Large-Scale Interconnection Network Simulator by Using GPU. CANDAR 2015: 585-589 - [c34]Kosuke Hiraishi, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota:
Proposal of Highly Efficient Memory Access Method Using Locked-Cache on Soft-Core Processor with SIMD Operations. CANDAR 2015: 595-597 - [c33]Hiroyuki Obuchi, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota:
Efficient Translation and Execution Method for Automated Parallel Processing System by Using Valgrind. CANDAR 2015: 607-609 - [c32]Yuki Sawada, Yusuke Arai, Kanemitsu Ootsu, Takashi Yokota, Takeshi Ohkawa:
An Android cluster system capable of dynamic node reconfiguration. ICUFN 2015: 689-694 - [c31]Kanemitsu Ootsu, Yutaka Matsuno, Takeshi Ohkawa, Takashi Yokota, Takanobu Baba:
Empirical performance study of speculative parallel processing on commercial multi-core CPU with hardware transactional memory. SEPS@SPLASH 2015: 57-65 - [i1]Kazushi Yamashina, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota:
Proposal of ROS-compliant FPGA Component for Low-Power Robotic Systems. CoRR abs/1508.07123 (2015) - 2013
- [j7]Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba:
An automatic thread decomposition approach for pipelined multithreading. Int. J. High Perform. Comput. Netw. 7(3): 227-237 (2013) - [j6]Takeshi Ohkawa, Daichi Uetake, Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba:
Reconfigurable and hardwired ORB engine on FPGA by Java-to-HDL synthesizer for realtime application. SIGARCH Comput. Archit. News 41(5): 77-82 (2013) - [c30]Takeshi Ohkawa, Takashi Yokota, Kanemitsu Ootsu:
A prototyping system for hardware distributed objects with diversity of programming languages design and preliminary evaluation. FPT 2013: 474-477 - [c29]Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa:
A Cellular Automata Approach for Large-Scale Interconnection Network Simulation. CANDAR 2013: 545-551 - [c28]Takayuki Hoshi, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota:
Runtime Overhead Reduction in Automated Parallel Processing System Using Valgrind. CANDAR 2013: 572-576 - [c27]Hiroyoshi Jutori, Takanobu Baba, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota:
Exploration of Highly Accurate Path Prediction Mechanism Using Detailed Path History. CANDAR 2013: 582-586 - [c26]Masayuki Omote, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota:
Efficient Data Communication Using Dynamic Switching of Compression Method. CANDAR 2013: 607-611 - 2012
- [c25]Kazuhiro Kinkai, Takanobu Baba, Hiroyoshi Jutori, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota
Comparative Study of Path Prediction Method for Speculative Loop Execution. ICNC 2012: 283-287 - [c24]Atsushi Shina, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota
Proposal of Incremental Software Simulation for Reduction of Evaluation Time. ICNC 2012: 311-315 - 2011
- [c23]Takashi Yokota
Steady/Unsteady Communication Performance in Large-Scale Regular Networks. AINA Workshops 2011: 727-732 - 2010
- [c22]Kanemitsu Ootsu, Takeshi Abe, Takashi Yokota
Loop Performance Improvement for Min-cut Program Decomposition Method. ICNC 2010: 78-87 - [c21]Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota
Automatic Thread Decomposition for Pipelined Multithreading. ICPADS 2010: 91-98
2000 – 2009
- 2009
- [j5]Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba:
A Quantitative Evaluation Methodology of Interconnection Networks. Inf. Media Technol. 4(4): 857-869 (2009) - [c20]Takashi Yokota
An Effective Throttling Method Based on Quasi-global Congestion Information. ISPAN 2009: 104-109 - [c19]Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota
Clustered Software Queue for Efficient Pipelined Multithreading. PDCAT 2009: 116-123 - 2008
- [c18]Takashi Yokota
Potentials of Branch Predictors: From Entropy Viewpoints. ARCS 2008: 273-285 - [c17]Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota
Clustered Decoupled Software Pipelining on Commodity CMP. ICPADS 2008: 681-688 - [c16]Takashi Yokota
Are Uniform Nerworks Scalable? PDCAT 2008: 137-140 - 2007
- [c15]Takashi Yokota
Introducing entropies for representing program behavior and branch predictor performance. Experimental Computer Science 2007: 17 - [c14]Takashi Yokota, Masaaki Ogawa, Kanemitsu Ootsu, Takamitsu Baba:
Quasi-global routing for fault-tolerant high-performance interconnection networks. Parallel and Distributed Computing and Networks 2007: 198-193 - [c13]Kanemitsu Ootsu, Takahiko Kobayashi, Takashi Yokota, Takanobu Baba:
A thread partitioning technique for multithreaded execution along hot paths. Parallel and Distributed Computing and Networks 2007: 278-282 - 2006
- [c12]Takashi Yokota, Kanemitsu Ootsu, Fumihito Furukawa, Takanobu Baba:
Entropy Throttling: A Physical Approach for Maximizing Packet Mobility in Interconnection Networks. Asia-Pacific Computer Systems Architecture Conference 2006: 309-322 - 2005
- [c11]Takashi Yokota, Masashi Nishitani, Kanemitsu Ootsu, Fumihito Furukawa, Takanobu Baba:
Cross-Line - A Globally Adaptive Control Method of Interconnection Network. ISHPC 2005: 191-198 - [c10]Takashi Yokota
Two-Path Limited Speculation Method for Static/Dynamic Optimization in Multithreaded Systems. PDCAT 2005: 46-50 - [c9]Atsushi Tsukikawa, Fumihito Furukawa, Takayuki Aoki, Daisuke Oka, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba:
Design and Implementation of a VLIW Processor Simulation Environment with Instruction Scheduling Framework. IASTED PDCS 2005: 536-541 - 2003
- [j4]Yoshiyuki Iwamoto, Koichi Suga, Kanemitsu Ootsu, Takashi Yokota
Receiving message prediction method. Parallel Comput. 29(11-12): 1509-1538 (2003) - 2002
- [c8]Takashi Yokota, Masamichi Nagafuchi, Yoshito Mekada, Tsutomu Yoshinaga, Kanemitsu Ootsu, Takanobu Baba:
A Scalable FPGA-Based Custom Computing Machine for a Medical Image Processing. FCCM 2002: 307-308 - [c7]Takashi Yokota, Masamichi Nagafuchi, Yoshito Mekada, Tsutomu Yoshinaga, Kanemitsu Ootsu, Takanobu Baba:
Real-Time Medical Diagnosis on a Multiple FPGA-based System. FPL 2002: 1088-1091 - [c6]Kanemitsu Ootsu, Takafumi Ono, Takashi Yokota, Takanobu Baba:
A Methodology of Binary-level Multithreading and Its Preliminary Evaluation. IASTED PDCS 2002: 792-797
1990 – 1999
- 1997
- [c5]Takashi Yokota, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono, Shuichi Sakai:
Virtual control channel and its application to the massively parallel computer RWC-1. HiPC 1997: 443-448 - 1996
- [c4]Kazuaki Okamoto, Shuichi Sakai, Hiroshi Matsuoka, Takashi Yokota, Hideo Hirono:
Multithread execution mechanisms on RICA-1 for massively parallel computation. IEEE PACT 1996: 116-121 - 1995
- [j3]Shuichi Sakai
Reduced Interprocessor-Communication Architecture and its Implementation on EM-4. Parallel Comput. 21(5): 753-769 (1995) - [c3]Takashi Yokota, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono, Atsushi Hori, Shuichi Sakai:
A prototype router for the massively parallel computer RWC-1. ICCD 1995: 279-284 - [c2]Atsushi Hori, Takashi Yokota, Yutaka Ishikawa, Shuichi Sakai
Time Space Sharing Scheduling and Architectural Support. JSSPP 1995: 92-105 - 1993
- [c1]Shuichi Sakai, Hiroshi Matsuoka, Yuetsu Kodama, Mitsuhisa Sato, Andrew Shaw, Hideo Hirono, Kazuaki Okamoto, Takashi Yokota:
RICA: Reduced Interprocessor-Communication Architecture - Concept and Mechanisms. SPDP 1993: 122-127
1980 – 1989
- 1987
- [j2]Takeshi Otsuka, Douglas Villaret, Takashi Yokota, Yutaka Takebe, Frank Lee, Naoko Arai, Ken-ichi Arai:
Structural analysis of the mouse chromosomal gene encoding interleukin 4 which expresses B cell, T cell and mast cell stimulating activities. Nucleic Acids Res. 15(1): 333-344 (1987) - 1986
- [j1]Takashi Yokota, Hideharu Amano, Hideo Aiso:
Dynamic fault recovery in mesh-connected parallel computers. Syst. Comput. Jpn. 17(7): 10-18 (1986)
Coauthor Index
[c62] [j19] [j18] [c61] [c60] [c59] [c58] [c57] [j17] [c55] [j16] [j15] [j14] [c54] [c53] [c52] [c51] [j13] [j12] [c50] [c49] [c48] [c47] [c46] [j11] [j10] [c45] [c44] [c43] [c42] [c41] [c40] [j9] [c39] [c38] [c37] [j8] [c36] [c35] [c34] [c33] [c32] [c31] [i1] [j7] [j6] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [j5] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [j4] [c8] [c7] [c6]
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last updated on 2024-09-07 01:02 CEST by the dblp team
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