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Takeshi Ohkawa
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2020 – today
- 2024
- [c45]Kenji Hisazumi, Takeshi Ohkawa, Masafumi Miwa, Mikiko Sato, Takashi Nagai
, Nobuhiro Ohe, Kittikhun Thongpull, Nattha Jindapetch, Harumi Watanabe:
APRIS Robot Challenge: Collaborative Online Interdisciplinary and International Learning for IoT/Robotics Systems. EDUCON 2024: 1-8 - [c44]Takeshi Ohkawa, Kenta Arai, Kanemitsu Ootsu, Takashi Yokota:
Alchemist: A Component-Oriented Development Tool of FPGA based on Publish/Subscribe Model. ICCE 2024: 1-6 - 2023
- [c43]Takeshi Ohkawa, Masahiro Aoyagi:
FPGA Emulation of Through-Silicon-Via (TSV) Dataflow Network for 3D Standard Chip Stacking System. COOL CHIPS 2023: 1-3 - [c42]Hayato Mori, Eisuke Okazaki, Gai Nagahashi, Mikiko Sato, Takeshi Ohkawa, Midori Sugaya:
Offloading Image Recognition Processing for Care Robots to FPGA on Multi-access Edge Computing. ICFPT 2023: 270-271 - 2022
- [c41]Hayato Mori, Hayato Amano, Akinobu Mizutani
Desgin and Implementation of ROS2-based Autonomous Tiny Robot Car with Integration of Multiple ROS2 FPGA Nodes. FPT 2022: 1-4 - [c40]Ludi Wang, Takeshi Ohkawa:
FPGA-Based Control of Remote Robotic Hands and ROS2 Integration. CANDARW 2022: 438-440 - [c39]Masato Fukui, Yoichi Ishiwata, Takeshi Ohkawa, Midori Sugaya:
IoT Edge Server ROS Node Allocation Method for Multi-SLAM on Many-core. PerCom Workshops 2022: 421-426 - 2021
- [j13]Koki Higashi, Yoichi Ishiwata, Takeshi Ohkawa, Midori Sugaya:
Fogcached-Ros: DRAM/NVMM Hybrid KVS Server with ROS Based Extension for ROS Application and SLAM Evaluation. IEICE Trans. Inf. Syst. 104-D(12): 2097-2108 (2021) - [c38]Sannomiya Natsuho, Takeshi Ohkawa, Hideharu Amano, Midori Sugaya:
Power Consumption Reduction Method and Edge Offload Server for Multiple Robots. EDGE 2021: 1-19 - [c37]Hayato Amano, Hayato Mori, Akinobu Mizutani
A dataset generation for object recognition and a tool for generating ROS2 FPGA node. FPT 2021: 1-4 - [c36]Chinatsu Yamamoto, Ikuta Tanigawa, Kenji Hisazumi, Mikiko Sato, Takeshi Ohkawa, Nobuhiko Ogura, Harumi Watanabe:
Layer Modeling and Its Code Generation based on Context-oriented Programming. MODELSWARD 2021: 330-336 - 2020
- [j12]Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa:
Genetic Node-Mapping Methods for Rapid Collective Communications. IEICE Trans. Inf. Syst. 103-D(1): 111-129 (2020) - [c35]Daniel Pinheiro Leal, Midori Sugaya, Hideharu Amano, Takeshi Ohkawa:
FPGA Acceleration of ROS2-Based Reinforcement Learning Agents. CANDAR (Workshops) 2020: 106-112 - [c34]Daniel Pinheiro Leal, Midori Sugaya, Hideharu Amano, Takeshi Ohkawa:
Automated Integration of High-Level Synthesis FPGA Modules with ROS2 Systems. FPT 2020: 292-293
2010 – 2019
- 2019
- [j11]Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa:
Accelerating Large-Scale Interconnection Network Simulation by Cellular Automata Concept. IEICE Trans. Inf. Syst. 102-D(1): 52-74 (2019) - [j10]Takeshi Ohkawa, Kazushi Yamashina, Takuya Matsumoto, Kanemitsu Ootsu, Takashi Yokota:
Automatic Generation Tool of FPGA Components for Robots. IEICE Trans. Inf. Syst. 102-D(5): 1012-1019 (2019) - [j9]Takanobu Baba, Shinpei Watanabe, Boaz Jessie Jackin
Fast Computation with Efficient Object Data Distribution for Large-Scale Hologram Generation on a Multi-GPU Cluster. IEICE Trans. Inf. Syst. 102-D(7): 1310-1320 (2019) - [c33]Masahiro Nissato, Hiroki Sugiyama, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota:
Realization and Preliminary Evaluation of MPI Runtime Environment on Android Cluster. AINA 2019: 407-418 - [c32]Takeshi Ohkawa, Shotaro Tayama, Hayato Mori, Dohyung Lee, Hayato Amano, Itsuki Hirakawa, Mikiko Sato, Harumi Watanabe:
Design and Development of Networked Multiple FPGA Components for Autonomous Tiny Robot Car. FPT 2019: 473-475 - [c31]Takeshi Ohkawa, Yuhei Sugata, Harumi Watanabe, Nobuhiko Ogura, Kanemitsu Ootsu, Takashi Yokota:
High level synthesis of ROS protocol interpretation and communication circuit for FPGA. RoSE@ICSE 2019: 33-36 - [c30]Takeshi Ohkawa, Ikuta Tanigawa, Mikiko Sato, Kenji Hisazumi
Prototype of FPGA Dynamic Reconfiguration Based-on Context-Oriented Programming. MCSoC 2019: 116-122 - [c29]Kengo Jingu, Kohta Shigenobu, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota:
Directive-Based Parallelization of For-Loops at LLVM IR Level. SNPD 2019: 421-426 - 2018
- [j8]Takeshi Ohkawa, Kazushi Yamashina, Hitomi Kimura, Kanemitsu Ootsu, Takashi Yokota:
FPGA Components for Integrating FPGAs into Robot Systems. IEICE Trans. Inf. Syst. 101-D(2): 363-375 (2018) - [j7]Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa:
A Genetic Approach for Accelerating Communication Performance by Node Mapping. IEICE Trans. Inf. Syst. 101-D(12): 2971-2975 (2018) - [c28]Hiromichi Wakatsuki, Takao Kido, Kenta Arai, Yuhei Sugata, Kanemitsu Ootsu, Takashi Yokota, Takeshi Ohkawa:
Development of a Robot Car by Single Line Search Method for White Line Detection with FPGA. FPT 2018: 415-418 - [c27]Kengo Jingu, Kohta Shigenobu, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota:
An Implementation of LLVM Pass for Loop Parallelization Based on IR-Level Directives. CANDAR Workshops 2018: 501-505 - [c26]Takanobu Baba, Shinpei Watanabe, Boaz Jessie Jackin
Data Distribution Method for Fast Giga-scale Hologram Generation on a Multi-GPU Cluster. ApPLIED@PODC 2018: 37-40 - [c25]Takanobu Baba, Shinpei Watanabe, Boaz Jessie Jackin
Overcoming the difficulty of large-scale CGH generation on multi-GPU cluster. GPGPU@PPoPP 2018: 13-21 - 2017
- [j6]Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa:
A Static Packet Scheduling Approach for Fast Collective Communication by Using PSO. IEICE Trans. Inf. Syst. 100-D(12): 2781-2795 (2017) - [j5]Yuki Sawada
Performance of Android Cluster System Allowing Dynamic Node Reconfiguration. Wirel. Pers. Commun. 93(4): 1067-1087 (2017) - [c24]Yuhei Sugata, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota:
Acceleration of Publish/Subscribe Messaging in ROS-compliant FPGA Component. HEART 2017: 13:1-13:6 - [c23]Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa:
Large-Scale Interconnection Network Simulation Methods Based on Cellular Automata. CANDAR 2017: 58-67 - [c22]Kohta Shigenobu, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota:
A Translation Method of ARM Machine Code to LLVM-IR for Binary Code Parallelization and Optimization. CANDAR 2017: 575-579 - [c21]Shinpei Watanabe, Boaz Jessie Jackin
Acceleration of Large-Scale CGH Generation Using Multi-GPU Cluster. CANDAR 2017: 589-593 - [c20]Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota, Katsuya Kikuchi, Masahiro Aoyagi:
Designing Efficient Parallel Processing in 3D Standard-Chip Stacking System with Standard Bus. MCSoC 2017: 128-135 - 2016
- [j4]Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa:
Enhancing Entropy Throttling: New Classes of Injection Control in Interconnection Networks. IEICE Trans. Inf. Syst. 99-D(12): 2911-2922 (2016) - [c19]Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa:
Introducing PSO for Optimal Packet Scheduling of Collective Communication. CANDAR 2016: 429-435 - [c18]Kazushi Yamashina, Hitomi Kimura, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota:
cReComp: Automated Design Tool for ROS-Compliant FPGA Component. MCSoC 2016: 138-145 - [c17]Takeshi Ohkawa, Kazushi Yamashina, Takuya Matsumoto, Kanemitsu Ootsu, Takashi Yokota:
Architecture exploration of intelligent robot system using ros-compliant FPGA component. RSP 2016: 72-78 - 2015
- [j3]Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa:
Relaxing Heavy Congestion by State Propagation. J. Inf. Process. 23(5): 730-743 (2015) - [c16]Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa:
Entropy Throttling: Towards Global Congestion Control of Interconnection Networks. CANDAR 2015: 40-49 - [c15]Yuki Suzuki, Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa:
Performance Improvement of Large-Scale Interconnection Network Simulator by Using GPU. CANDAR 2015: 585-589 - [c14]Kosuke Hiraishi, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota:
Proposal of Highly Efficient Memory Access Method Using Locked-Cache on Soft-Core Processor with SIMD Operations. CANDAR 2015: 595-597 - [c13]Hiroyuki Obuchi, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota:
Efficient Translation and Execution Method for Automated Parallel Processing System by Using Valgrind. CANDAR 2015: 607-609 - [c12]Yuki Sawada, Yusuke Arai, Kanemitsu Ootsu, Takashi Yokota, Takeshi Ohkawa:
An Android cluster system capable of dynamic node reconfiguration. ICUFN 2015: 689-694 - [c11]Kanemitsu Ootsu, Yutaka Matsuno, Takeshi Ohkawa, Takashi Yokota, Takanobu Baba:
Empirical performance study of speculative parallel processing on commercial multi-core CPU with hardware transactional memory. SEPS@SPLASH 2015: 57-65 - [i1]Kazushi Yamashina, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota:
Proposal of ROS-compliant FPGA Component for Low-Power Robotic Systems. CoRR abs/1508.07123 (2015) - 2013
- [j2]Takeshi Ohkawa, Daichi Uetake, Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba:
Reconfigurable and hardwired ORB engine on FPGA by Java-to-HDL synthesizer for realtime application. SIGARCH Comput. Archit. News 41(5): 77-82 (2013) - [c10]Takeshi Ohkawa, Takashi Yokota, Kanemitsu Ootsu:
A prototyping system for hardware distributed objects with diversity of programming languages design and preliminary evaluation. FPT 2013: 474-477 - [c9]Takashi Yokota, Kanemitsu Ootsu, Takeshi Ohkawa:
A Cellular Automata Approach for Large-Scale Interconnection Network Simulation. CANDAR 2013: 545-551 - [c8]Takayuki Hoshi, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota:
Runtime Overhead Reduction in Automated Parallel Processing System Using Valgrind. CANDAR 2013: 572-576 - [c7]Hiroyoshi Jutori, Takanobu Baba, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota:
Exploration of Highly Accurate Path Prediction Mechanism Using Detailed Path History. CANDAR 2013: 582-586 - [c6]Masayuki Omote, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota:
Efficient Data Communication Using Dynamic Switching of Compression Method. CANDAR 2013: 607-611 - 2012
- [c5]Kazuhiro Kinkai, Takanobu Baba, Hiroyoshi Jutori, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota
Comparative Study of Path Prediction Method for Speculative Loop Execution. ICNC 2012: 283-287 - [c4]Atsushi Shina, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota
Proposal of Incremental Software Simulation for Reduction of Evaluation Time. ICNC 2012: 311-315 - 2011
- [c3]Marco Chacin, Hiroyuki Uchida, Michiya Hagimoto, Takashi Miyazaki, Takeshi Ohkawa, Rimon Ikeno, Yukoh Matsumoto, Fumito Imura, Motohiro Suzuki, Katsuya Kikuchi, Hiroshi Nakagawa, Masahiro Aoyagi:
COOL interconnect low power interconnection technology for scalable 3D LSI design. COOL Chips 2011: 1-3 - 2010
- [j1]Koichi Ono, Takeshi Ohkawa, Masahiro Segami, Masao Hotta:
A Cascaded Folding ADC Based on Fast-Settling 3-Degree Folders with Enhanced Reset Technique. IEICE Trans. Electron. 93-C(3): 288-294 (2010)
2000 – 2009
- 2004
- [c2]Takeshi Ohkawa, Toshiyuki Nozawa, Masanori Fujibayashi, Naoto Miyamoto, Leo Karnan, Soichiro Kita, Koji Kotani, Tadahiro Ohmi:
The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration. ASP-DAC 2004: 557-558 - [c1]Md. Ashfaquzzaman Khan, Naoto Miyamoto, Takeshi Ohkawa, Amir Jamak, Soichiro Kita, Koji Kotani, Tadahiro Ohmi:
An approach to realize time-sharing of flip-flops in time-multiplexed FPGAs. FPT 2004: 351-354
Coauthor Index
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