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"A Transistor Level Placement Tool for Custom Cell Generation."

Ranjit K. Dash et al. (2000)

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DOI: 10.1109/ICVD.2000.812617

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/vlsid/DashPVR00
Ranjit K. Dash, T. Pramod, Vinita Vasudevan, M. Ramakrishna:
A Transistor Level Placement Tool for Custom Cell Generation. VLSI Design 2000: 254-257

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