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Anirudh Devgan
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2000 – 2009
- 2009
- [c44]Anirudh Devgan, Bülent Basaran, David Colleran, Mar Hershenson:
Accelerated design of analog, mixed-signal circuits in Titan. ISPD 2009: 67-72 - 2008
- [c43]Sachin S. Sapatnekar, Eshel Haritan, Kurt Keutzer, Anirudh Devgan, Desmond Kirkpatrick, Stephen Meier, Duaine Pryor, Tom Spyrou:
Reinventing EDA with manycore processors. DAC 2008: 126-127 - 2007
- [j14]Anand Ramalingam, Anirudh Devgan, David Z. Pan:
Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce. J. Low Power Electron. 3(1): 28-35 (2007) - [j13]Murari Mani, Anirudh Devgan, Michael Orshansky, Yaping Zhan:
A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10): 1790-1802 (2007) - 2006
- [j12]Rajeev R. Rao, Anirudh Devgan, David T. Blaauw, Dennis Sylvester:
Analytical yield prediction considering leakage/performance correlation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1685-1695 (2006) - [c42]Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan:
Robust analytical gate delay modeling for low voltage circuits. ASP-DAC 2006: 61-66 - 2005
- [j11]Rajeev R. Rao, David T. Blaauw, Dennis Sylvester, Anirudh Devgan:
Modeling and Analysis of Parametric Yield under Power and Performance Constraints. IEEE Des. Test Comput. 22(4): 376-385 (2005) - [j10]Emrah Acar, Anirudh Devgan, Sani R. Nassif:
Leakage and Leakage Sensitivity Computation for Combinational Circuits. J. Low Power Electron. 1(2): 172-181 (2005) - [c41]Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Anirudh Devgan:
Achieving continuous VT performance in a dual VT process. ASP-DAC 2005: 393-398 - [c40]David T. Blaauw, Anirudh Devgan, Farid N. Najm:
Leakage power: trends, analysis and avoidance. ASP-DAC 2005 - [c39]Anand Ramalingam, Bin Zhang, Anirudh Devgan, David Z. Pan:
Sleep transistor sizing using timing criticality and temporal currents. ASP-DAC 2005: 1094-1097 - [c38]Michael W. Beattie, Hui Zheng, Anirudh Devgan, Byron Krauter:
Spatially distributed 3D circuit models. DAC 2005: 153-158 - [c37]Murari Mani, Anirudh Devgan, Michael Orshansky:
An efficient algorithm for statistical minimization of total power under timing yield constraints. DAC 2005: 309-314 - [c36]Florentin Dartu, Anirudh Devgan, Noel Menezes:
Variability modeling and variability-aware design in deep submicron integrated circuits. ACM Great Lakes Symposium on VLSI 2005: 1 - [c35]Maha Nizam, Farid N. Najm, Anirudh Devgan:
Power grid voltage integrity verification. ISLPED 2005: 239-244 - [c34]Anirudh Devgan, Ruchir Puri, Sachin Sapatnaker, Tanay Karnik, Rajiv V. Joshi:
Design of sub-90nm Circuits and Design Methodologies. ISQED 2005: 3-4 - [c33]Anirudh Devgan, Luca Daniel, Byron Krauter, Lei He:
Modeling and Design of Chip-Package Interface. ISQED 2005: 6 - [c32]Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka
, Dennis Sylvester, Richard B. Brown:
Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. ISQED 2005: 284-290 - [c31]Anirudh Devgan, Sani R. Nassif:
Power Variability and Its Impact on Design. VLSI Design 2005: 679-682 - 2004
- [j9]Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan:
Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 509-516 (2004) - [j8]Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan:
Closed-form delay and slew metrics made easy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12): 1661-1669 (2004) - [c30]Rajeev R. Rao, Anirudh Devgan, David T. Blaauw, Dennis Sylvester:
Parametric yield estimation considering leakage variability. DAC 2004: 442-447 - [c29]Rajiv V. Joshi, Saibal Mukhopadhyay, Donald W. Plass, Yuen H. Chan, Ching-Te Chuang, Anirudh Devgan:
Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell. ESSCIRC 2004: 211-214 - 2003
- [c28]Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan:
Delay and slew metrics using the lognormal distribution. DAC 2003: 382-385 - [c27]Jiayong Le, Lawrence T. Pileggi, Anirudh Devgan:
Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics. ICCAD 2003: 491-496 - [c26]Anirudh Devgan, Chandramouli V. Kashyap:
Block-based Static Timing Analysis with Uncertainty. ICCAD 2003: 607-614 - [c25]Haihua Su, Frank Liu, Anirudh Devgan, Emrah Acar, Sani R. Nassif:
Full chip leakage estimation considering power supply and temperature variations. ISLPED 2003: 78-83 - [c24]Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns:
Leakage and leakage sensitivity computation for combinational circuits. ISLPED 2003: 96-99 - [c23]Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown:
Efficient techniques for gate leakage estimation. ISLPED 2003: 100-103 - [c22]Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan:
Closed form expressions for extending step delay and slew metrics to ramp inputs. ISPD 2003: 24-31 - 2002
- [j7]Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay:
Correction to "interconnect synthesis without wire tapering". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(4): 497-497 (2002) - [c21]Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan:
PERI: a technique for extending delay and slew metrics to ramp inputs. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 57-62 - 2001
- [j6]Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay:
Interconnect synthesis without wire tapering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1): 90-104 (2001) - [j5]Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap:
RC delay metrics for performance optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(5): 571-582 (2001) - [c20]Hao Ji, Anirudh Devgan, Wayne Wei-Ming Dai:
KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect. ASP-DAC 2001: 379-384 - 2000
- [j4]Tuyen V. Nguyen, Anirudh Devgan, Ognen J. Nastov, David W. Winston:
Transient sensitivity computation in controlled explicit piecewiselinear simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(1): 98-110 (2000) - [c19]Anirudh Devgan, Hao Ji, Wayne Wei-Ming Dai:
How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K. ICCAD 2000: 150-155 - [c18]Chandramouli V. Kashyap, Charles J. Alpert, Anirudh Devgan:
An "Effective" Capacitance Based Delay Metric for RC Interconnect. ICCAD 2000: 229-234 - [c17]Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap:
A two moment RC delay metric for performance optimization. ISPD 2000: 69-74
1990 – 1999
- 1999
- [j3]Charles J. Alpert, Anirudh Devgan, Stephen T. Quay:
Buffer insertion for noise and delay optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(11): 1633-1645 (1999) - [c16]Charles J. Alpert, Anirudh Devgan, Stephen T. Quay:
Buffer Insertion with Accurate Gate and Interconnect Delay Computation. DAC 1999: 479-484 - [c15]Anirudh Devgan, Peter R. O'Brien:
Realizable reduction for RC interconnect circuits. ICCAD 1999: 204-207 - [c14]Charles J. Alpert, Anirudh Devgan, Stephen T. Quay:
Is wire tapering worthwhile? ICCAD 1999: 430-436 - 1998
- [c13]Anirudh Devgan, Sandip Kundu:
Timing Analysis and Optimization: From Devices to Systems (Abstract of Embedded Tutorial). ASP-DAC 1998: 345 - [c12]Charles J. Alpert, Anirudh Devgan, Stephen T. Quay:
Buffer Insertion for Noise and Delay Optimization. DAC 1998: 362-367 - [c11]Tuyen V. Nguyen, Anirudh Devgan, Ognen J. Nastov:
Adjoint Transient Sensitivity Computation in Piecewise Linear Simulation. DAC 1998: 477-482 - [c10]Tuyen V. Nguyen, Anirudh Devgan, Ali Sadigh:
Simulation of coupling capacitances using matrix partitioning. ICCAD 1998: 12-18 - 1997
- [c9]Charles J. Alpert, Anirudh Devgan:
Wire Segmenting for Improved Buffer Insertion. DAC 1997: 588-593 - [c8]Anirudh Devgan:
Efficient coupled noise estimation for on-chip interconnects. ICCAD 1997: 147-151 - [c7]Anirudh Devgan, Leon Stok, Sandip Kundu:
Timing analysis and optimization: from devices to systems (tutorial). ICCAD 1997 - [c6]Tuyen V. Nguyen, Anirudh Devgan:
State transformation in event driven explicit simulation. ICCAD 1997: 289-294 - 1996
- [j2]Anirudh Devgan:
Transient simulation of integrated circuits in the charge-voltage plane. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(11): 1379-1390 (1996) - 1995
- [c5]Anirudh Devgan:
Efficient and accurate transient simulation in charge-voltage plane. ICCAD 1995: 110-114 - [c4]Anirudh Devgan:
Accurate device modeling techniques for efficient timing simulation of integrated circuits. ICCD 1995: 138-143 - [c3]Anirudh Devgan, Ronald A. Rohrer:
Efficient simulation of interconnect and mixed analog-digital circuits in ACES. VLSI Design 1995: 229-233 - 1994
- [j1]Anirudh Devgan, Ronald A. Rohrer:
Adaptively controlled explicit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(6): 746-762 (1994) - 1993
- [c2]Anirudh Devgan, Ronald A. Rohrer:
Event driven adaptively controlled explicit simulation of integrated circuits. ICCAD 1993: 136-140 - [c1]Anirudh Devgan, Ronald A. Rohrer:
ACES: A Transient Simulation Strategy for Integrated Circuits. ICCD 1993: 357-360
Coauthor Index
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