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Hiroto Yasuura
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2010 – 2019
- 2017
- [c81]Hiroto Yasuura:
ASP-DAC 2017 keynote speech I-3: Design of society: Beyond digital system design. ASP-DAC 2017: 4 - 2012
- [j33]Yuji Kunitake, Toshinori Sato
, Hiroto Yasuura
A Selective Replacement Method for Timing-Error-Predicting flip-Flops. J. Circuits Syst. Comput. 21(6) (2012) - [c80]Atsushi Shimada
WiP Abstract: Estimation of Electric Power Consumption of Individuals by Observing People's Activity. ICCPS 2012: 206 - [c79]Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura
Neutron-induced soft error rate estimation for SRAM using PHITS. IOLTS 2012: 138-141 - [c78]Yuji Kunitake, Toshinori Sato
Guidelines for mitigating NBTI degradation in on-chip memories. ISCIT 2012: 822-827 - 2011
- [j32]Yuji Kunitake, Toshinori Sato
Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI. IEICE Trans. Electron. 94-C(4): 520-529 (2011) - [j31]Shunsuke Inenaga, Kenichirou Oyama, Hiroto Yasuura:
Towards Modeling Stored-value Electronic Money Systems. Inf. Media Technol. 6(1): 25-34 (2011) - [j30]Toru Nakamura, Shunsuke Inenaga, Daisuke Ikeda, Kensuke Baba, Hiroto Yasuura:
Password Based Anonymous Authentication with Private Information Retrieval. J. Digit. Inf. Manag. 9(2): 72-78 (2011) - [c77]Toru Nakamura, Shunsuke Inenaga, Kensuke Baba, Daisuke Ikeda, Hiroto Yasuura:
An Anonymous Authentication Protocol with Single-database PIR. AISC 2011: 3-8 - [c76]Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura
Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS 2011: 151-156 - 2010
- [j29]Yuriko Ishitobi, Tohru Ishihara
Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories. J. Signal Process. Syst. 60(2): 211-224 (2010) - [c75]Ashir Ahmed
An Information Platform for Low-Literate Villagers. AINA 2010: 1271-1277 - [c74]Toru Nakamura, Shunsuke Inenaga, Daisuke Ikeda, Kensuke Baba, Hiroto Yasuura:
An Identifiable Yet Unlinkable Authentication System with Smart Cards for Multiple Services. ICCSA (4) 2010: 236-251 - [c73]Yuji Kunitake, Toshinori Sato
Signal probability control for relieving NBTI in SRAM cells. ISQED 2010: 660-666 - [c72]Yuji Kunitake, Toshinori Sato
A Replacement Strategy for Canary Flip-Flops. PRDC 2010: 227-228 - [c71]Naotaka Maruyama, Tohru Ishihara
An RTOS in hardware for energy efficient software-based TCP/IP processing. SASP 2010: 58-63
2000 – 2009
- 2009
- [j28]Yuji Kunitake, Kazuhiro Mima, Toshinori Sato
Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment. IEICE Trans. Electron. 92-C(4): 483-491 (2009) - [j27]Seiichiro Yamaguchi, Yuriko Ishitobi, Tohru Ishihara
Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion. IPSJ Trans. Syst. LSI Des. Methodol. 2: 189-199 (2009) - [j26]Tadayuki Matsumura, Tohru Ishihara
An Optimization Technique for Low-Energy Embedded Memory Systems. IPSJ Trans. Syst. LSI Des. Methodol. 2: 239-249 (2009) - [c70]Shuichi Sakai
Dependable VLSI: device, design and architecture: how should they cooperate? ASP-DAC 2009: 859-860 - [c69]Noriaki Sakamoto, Mitsuaki Fukase, Tsunenori Mine, Shigeru Kusakabe, Tsuneo Nakanishi, Yoichi Omori, Mohammad Mesbah Uddin, Keijiro Araki, Akira Fukuda, Hiroto Yasuura, Teruaki Kitasuka:
Large Scale Business-academia Collaboration in Master Education Course. CSEDU (2) 2009: 159-166 - [c68]Shunsuke Inenaga, Kenichirou Oyama, Hiroto Yasuura
Towards Modeling Stored-value Electronic Money Systems. NaBIC 2009: 902-907 - [c67]Tomomi Yamasaki, Shunsuke Inenaga, Daisuke Ikeda, Hiroto Yasuura:
Modeling Costs of Access Control with Various Key Management Systems. PDPTA 2009: 676-682 - 2008
- [j25]Mohammad Mesbah Uddin, Yasunobu Nohara
A Multi-Application Smart Card System with Authentic Post-Issuance Program Modification. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(1): 229-235 (2008) - [j24]Maziar Goudarzi
A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die Vth variation. Microelectron. J. 39(12): 1797-1808 (2008) - [c66]Yasunobu Nohara
A Secure High-Speed Identification Scheme for RFID Using Bloom Filters. ARES 2008: 717-722 - [c65]Tadayuki Matsumura, Tohru Ishihara
Simultaneous optimization of memory configuration and code allocation for low power embedded systems. ACM Great Lakes Symposium on VLSI 2008: 403-406 - [c64]Mohammad Mesbah Uddin, Salahuddin Muhammad Salim Zabir, Yasunobu Nohara, Hiroto Yasuura:
A Framework of Authentic Post-Issuance Program Modification for Multi-Application Smart Cards. ICWN 2008: 288-294 - [c63]Masanori Muroyama, Tohru Ishihara
Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption. PATMOS 2008: 62-71 - [c62]Shinsuke Ohtsuka, Satoshi Kawamoto, Shigeru Takano, Kensuke Baba, Hiroto Yasuura:
A Note on Biometrics-based Authentication with Portable Device. SECRYPT 2008: 99-102 - 2007
- [c61]Maziar Goudarzi
A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation. ASP-DAC 2007: 878-883 - [c60]Yuriko Ishitobi, Tohru Ishihara
Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories. ESTIMedia 2007: 13-18 - [c59]Tomomi Yamasaki, Toru Nakamura, Kensuke Baba
A Door Access Control System with Mobile Phones. PWC 2007: 230-240 - [c58]Yasunobu Nohara
Unlinkability and Real World Constraints in RFID Systems. PerCom Workshops 2007: 371-376 - [c57]Adil El Bourichi, Hiroto Yasuura
A low complexity and energy efficient dynamic channel allocation algorithm for multiuser OFDM. WTS 2007: 1-5 - 2006
- [j23]Yasunobu Nohara, Toru Nakamura, Kensuke Baba, Sozo Inoue, Hiroto Yasuura:
Unlinkable Identification for Large-scale RFID Systems. Inf. Media Technol. 1(2): 1182-1190 (2006) - [c56]Sozo Inoue, Hiroto Yasuura
Systematic Error Detection for RFID Reliability. ARES 2006: 280-286 - [c55]Donghoon Lee, Tohru Ishihara
An Energy Characterization Framework for Software-Based Embedded Systems. ESTIMedia 2006: 59-64 - [c54]Takahiro Watanabe, Yasunobu Nohara
On Authentication between Human and Computer. PerCom Workshops 2006: 636-639 - 2005
- [j22]Kosuke Tarumi, Akihiko Hyodo, Masanori Muroyama, Hiroto Yasuura
Bitwidth Optimization for Low Power Digital FIR Filter Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(4): 869-875 (2005) - [j21]Hiroto Yasuura
Special Section on Papers Selected from AP-ASIC 2004. IEICE Trans. Electron. 88-C(8): 1704 (2005) - [c53]Takahiro Watanabe, Sozo Inoue, Hiroto Yasuura
An RFID-based multi-service system for supporting conference events. AMT 2005: 435-439 - [c52]Masanori Muroyama, Kosuke Tarumi, Koji Makiyama, Hiroto Yasuura:
A variation-aware low-power coding methodology for tightly coupled buses. ASP-DAC 2005: 557-560 - [c51]Yasunobu Nohara
Toward Unlinkable ID Management for Multi-Service Environments. PerCom Workshops 2005: 115-119 - [c50]Yasunobu Nohara, Sozo Inoue, Kensuke Baba, Hiroto Yasuura:
Quantitative evaluation of unlinkable ID matching schemes. WPES 2005: 55-60 - 2004
- [c49]Hiroto Yasuura:
Digitally Named World: Challenges for New Social Infrastructures. ISQED 2004: 323 - 2003
- [j20]Takashi Yamada, Takeshi Sakamoto, Shinji Furuichi, Mamoru Mukuno, Yoshifumi Matsushita, Hiroto Yasuura:
Pre-Route Power Analysis Techniques for SoC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(3): 686-692 (2003) - [j19]Takashi Yamada, Atsushi Sakai, Yoshifumi Matsushita, Hiroto Yasuura:
Routing Methodology for Minimizing Crosstalk in SoC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(9): 2347-2356 (2003) - [j18]Akihiko Hyodo, Masanori Muroyama, Hiroto Yasuura:
Variable Pipeline Depth Processor for Energy Efficient Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 2983-2990 (2003) - [j17]Yun Cao, Hiroto Yasuura:
Leakage Power Reduction for Battery-Operated Portable Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3200-3203 (2003) - [j16]Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura
Reduction of coupling effects by optimizing the 3-D configuration of the routing grid. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 951-954 (2003) - [c48]Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura:
Reduction of crosstalk noise by optimizing 3-D configuration of the routing grid. ASP-DAC 2003: 49-52 - [c47]Yun Cao, Hiroto Yasuura:
Quality-driven design by bitwidth optimization for video applications. ASP-DAC 2003: 532-537 - [c46]Hiroto Yasuura
Towards the Digitally Named World -Challenges for New Social Infrastructures based on Information Technologies. DSD 2003: 17-22 - [c45]Masanori Muroyama, Akihiko Hyodo, Takanori Okuma, Hiroto Yasuura
A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits. DSD 2003: 408-415 - [c44]Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura:
Routing methodology for minimizing 1nterconnect energy dissipation. ACM Great Lakes Symposium on VLSI 2003: 120-123 - [e3]Hiroto Yasuura:
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003. ACM 2003, ISBN 0-7803-7660-9 [contents] - 2002
- [j15]Yun Cao, Hiroto Yasuura:
Quality-Driven Design for Video Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2568-2576 (2002) - [c43]Shoji Goto, Takashi Yamada, Norihisa Takayarna, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura
A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA. DSD 2002: 210-217 - [c42]Takanori Okuma, Yun Cao, Masanori Muroyama, Hiroto Yasuura:
Reducing access energy of on-chip data memory considering active data bitwidth. ISLPED 2002: 88-91 - [c41]Takeshi Sakamoto, Takashi Yamada, Mamoru Mukuno, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura:
Power analysis techniques for SoC with improved wiring models. ISLPED 2002: 259-262 - [c40]Shoji Goto, Takashi Yamada, Norihisa Takayama, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura:
A low-power digital matched filter for spread-spectrum systems. ISLPED 2002: 301-306 - [c39]Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin:
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems. ISSS 2002: 32-37 - [c38]Hiroto Yasuura, Naofumi Takagi, Srivaths Ravi, Michael Torla, Catherine H. Gebotys:
Special Session: Security on SoC. ISSS 2002: 192-194 - [c37]Hiroto Yasuura, Hiroyuki Tomiyama, Takanori Okuma, Yun Cao:
Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems. ISSS 2002: 201-206 - [c36]Masanori Muroyama, Tohru Ishihara
A Power Minimization Technique for Arithmetic Circuits by Cell Selection. ASP-DAC/VLSI Design 2002: 268-273 - [c35]Makoto Sugihara, Hiroto Yasuura
Optimization of Test Accesses with a Combined BIST and External Test Scheme. ASP-DAC/VLSI Design 2002: 683-688 - 2001
- [j14]Takanori Okuma, Hiroto Yasuura
Software Energy Reduction Techniques for Variable-Voltage Processors. IEEE Des. Test Comput. 18(2): 31-41 (2001) - [j13]Barry Shackleford, Greg Snider, Richard J. Carter, Etsuko Okushi, Mitsuhiro Yasuda, Katsuhiko Seo, Hiroto Yasuura:
A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine. Genet. Program. Evolvable Mach. 2(1): 33-60 (2001) - [c34]Yun Cao, Hiroto Yasuura:
A system-level energy minimization approach using datapath width optimization. ISLPED 2001: 231-236 - 2000
- [j12]Hiroto Yasuura:
Editorial. Des. Autom. Embed. Syst. 5(2): 127 (2000) - [j11]Akihiko Inoue, Tohru Ishihara
Flexible System LSI for Embedded Systems and Its Optimization Techniques. Des. Autom. Embed. Syst. 5(2): 179-205 (2000) - [c33]Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura
One language or more?: how can we design an SoC at a system level? ASP-DAC 2000: 653-654 - [c32]Makoto Sugihara, Hiroto Yasuura
Analysis and Minimization of Test Time in a Combined BIST and External Test Approach. DATE 2000: 134-140 - [c31]Kei Hirose, Hiroto Yasuura
A Bus Delay Reduction Technique Considering Crosstalk. DATE 2000: 441-445 - [c30]Tohru Ishihara
A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors. DATE 2000: 617-623 - [c29]Barry Shackleford, Etsuko Okushi, Mitsuhiro Yasuda, Hisao Koizumi, Katsuhiko Seo, Takashi Iwamoto, Hiroto Yasuura:
An FPGA-based genetic algorithm machine (poster abstract). FPGA 2000: 218 - [c28]Hajime Yamashita, Hiroto Yasuura, Eko Fajar, Yun Cao:
Variable size analysis and validation of computation quality. HLDVT 2000: 95-100 - [c27]Victor M. Goulart Ferreira, Hiroto Yasuura:
Functional Redundancy for Dynamic Exploitation of Performance-Energy Consumption Trade-Offs. SBCCI 2000: 165-170
1990 – 1999
- 1999
- [c26]Takanori Okuma, Tohru Ishihara, Hiroto Yasuura:
Real-Time Task Scheduling for a Variable Voltage Processor. ISSS 1999: 24-29 - 1998
- [j10]Hiroto Yasuura, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar:
Embedded System Design Using Soft-Core Processor and Valen-C. J. Inf. Sci. Eng. 14(3): 587-603 (1998) - [c25]Hiroyuki Tomiyama, Hiroto Yasuura:
Module Selection Using Manufacturing Information. ASP-DAC 1998: 275-281 - [c24]Tohru Ishihara, Hiroto Yasuura:
Power-Pro: Programmable Power Management Architecture. ASP-DAC 1998: 321-322 - [c23]Hiroyuki Tomiyama, Tohru Ishihara
Instruction Scheduling for Power Reduction in Processor-Based System Design. DATE 1998: 855-860 - [c22]Tohru Ishihara, Hiroto Yasuura:
Voltage scheduling problem for dynamically variable voltage processors. ISLPED 1998: 197-202 - [c21]Hiroyuki Tomiyama, Akihiko Inoue, Hiroto Yasuura:
Statistical Performance-Driven Module Binding in High-Level Synthesis. ISSS 1998: 66-71 - [c20]Takanori Okuma, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar, Hiroto Yasuura:
Instruction Encoding Techniques for Area Minimization of Instruction ROM. ISSS 1998: 125-130 - [c19]Makoto Sugihara, Hiroshi Date, Hiroto Yasuura
A novel test methodology for core-based system LSIs and a testing time minimization problem. ITC 1998: 465-472 - [e2]Hiroto Yasuura:
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1998, San Jose, CA, USA, November 8-12, 1998. ACM / IEEE Computer Society 1998, ISBN 1-58113-008-2 [contents] - 1997
- [j9]Hiroyuki Tomiyama, Hiroto Yasuura
Code placement techniques for cache miss rate reduction. ACM Trans. Design Autom. Electr. Syst. 2(4): 410-429 (1997) - [c18]Fumio Suzuki, Hisao Koizumi, M. Hiramine, K. Yamamoto, Hiroto Yasuura, K. Okino:
A HW/SW co-design environment for multi-media equipments development using inverse problem. CODES 1997: 153-157 - [c17]Barry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama, Hiroto Yasuura:
Memory-CPU Size Optimization for Embedded System Designs. DAC 1997: 246-251 - [c16]Barry Shackleford, Etsuko Okushi, Mitsuhiro Yasuda, Hisao Koizumi, Katsuhiko Seo, Takashi Iwamoto, Hiroto Yasuura:
A High-Performance Hardware Implementation of a Survival-Based Genetic Algorithm. ICONIP (1) 1997: 686-691 - [e1]Ralph H. J. M. Otten, Hiroto Yasuura:
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997. IEEE Computer Society / ACM 1997, ISBN 0-8186-8200-0 [contents] - 1996
- [j8]Tetsuya Yamada, Hiroto Yasuura
On the Computational Power of Binary Decision Diagram with Redundant Variables. Formal Methods Syst. Des. 8(1): 65-89 (1996) - [c15]Hiroyuki Tomiyama, Hiroto Yasuura
Optimal Code Placement of Embedded Software for Instruction Caches. ED&TC 1996: 96-101 - [c14]Tohru Ishihara, Hiroto Yasuura:
Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. ISLPED 1996: 117-120 - [c13]Hiroyuki Tomiyama, Hiroto Yasuura:
Size-Constrained Code Placement for Cache Miss Rate Reduction. ISSS 1996: 96-104 - 1995
- [j7]Hiroto Yasuura:
Foreword. IEICE Trans. Inf. Syst. 78-D(3): 197-198 (1995) - [j6]Hisao Koizumi, Katsuhiko Seo, Fumio Suzuki, Yoshisuke Ohtsuru, Hiroto Yasuura:
A Proposal for a Co-design Method in Control Systems Using Combination of Models. IEICE Trans. Inf. Syst. 78-D(3): 237-247 (1995) - 1994
- [c12]Nikil D. Dutt
Design Reuse: Fact or Fiction? (Panel). DAC 1994: 562 - 1993
- [c11]Takashi Hashimoto, Kazuaki J. Murakami, Tetsuo Hironaka, Hiroto Yasuura
A Micro-Vectorprocessor Architecture: Performance Modeling and Benchmarking. International Conference on Supercomputing 1993: 308-317 - 1992
- [c10]Vasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura:
Design of data-path module generators from algorithmic representations. Synthesis for Control Dominated Circuits 1992: 183-192 - 1990
- [c9]Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima:
NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I. DAC 1990: 8-13 - [c8]M. Ohmura, Hiroto Yasuura, Keikichi Tamaru:
Extraction of Functional Information from Combinatorial Circuits. ICCAD 1990: 176-179 - [c7]Hiroto Yasuura, Nagisa Ishiura:
Formal semantics of UDL/I and its applications to CAD/DA tools. ICCD 1990: 90-94
1980 – 1989
- 1989
- [c6]Hiroto Yasuura
Locally Computable Coding for Unary Operations. Concurrency: Theory, Language, And Architecture 1989: 312-323 - [c5]Hiroto Yasuura, Nagisa Ishiura:
Semantics of a Hardware Design Language for Japanese Standardization. DAC 1989: 836-839 - 1987
- [j5]Hiroto Yasuura
On high-speed parallel algorithms using redundant coding. Syst. Comput. Jpn. 18(12): 72-80 (1987) - [j4]Nagisa Ishiura, Hiroto Yasuura
High-Speed Logic Simulation on Vector Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(3): 305-321 (1987) - 1985
- [j3]Naofumi Takagi
High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree. IEEE Trans. Computers 34(9): 789-796 (1985) - 1984
- [c4]Hiroto Yasuura:
On Parallel Computational Complexity of Unification. FGCS 1984: 235-243 - [c3]Hiroto Yasuura, Shuzo Yajima:
Hardware Algorithms for VLSI Systems. VLSI Engineering 1984: 105-129 - 1982
- [j2]Hiroto Yasuura
The Parallel Enumeration Sorting Scheme for VLSI. IEEE Trans. Computers 31(12): 1192-1201 (1982) - [c2]Takeshi Sakai, Yoshiyuki Tsuchida, Hiroto Yasuura, Yasushi Ooi, Yoshitsugu Ono, Hiroshi Kano, Shinji Kimura, Shuzo Yajima:
An Interactive Simulation System for structured logic design - ISS. DAC 1982: 747-754 - [c1]Shuzo Yajima, Hiroto Yasuura
Hardware Algorithms and Logic Design Automation. An Overview and Progress Report. RIMS Symposium on Software Science and Engineering 1982: 147-164 - 1981
- [j1]Hiroto Yasuura
Width and Depth of Combinational Logic Circuits. Inf. Process. Lett. 13(4/5): 191-194 (1981)
Coauthor Index
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