default search action
Journal of Information Science and Engineering, Volume 14
Volume 14, Number 1, March 1998
- Jing-Chiou Liou, Michael A. Palis:
On the Effectiveness of Compiler-Time Scheduling Approaches for Distributed Memory Multiprocessor. 7-26 - Sandeep K. S. Gupta, S. Krishnamurthy:
An Interprocedural Framework for Determining Efficient Array Data Redistributeions. 27-51 - Chien-Min Wang, Yomin Hou, Chiu-Yu Ku:
Compiler Techniques for Minimizing Link Contention of Linear-Constant Communication on k-ary n-cubes. 53-78 - Pangfeng Liu, Jan-Jan Wu:
Supporting Efficieent Tree Structures for Distributed Scientific Computation. 79-105 - Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Meenakshi A. Kandaswamy:
Locality Optimization Algorithms for Compilation of Out-of-Core Codes. 107-138 - Yin-Tsung Hwang, Jer-Sho Hwang:
Simulated Evolution Based Parallel Code Generation for Programmable DSP Processors. 139-165 - Frederic Desprez, Jack J. Dongarra, Fabrice Rastello, Yves Robert:
Determining the Idle Time of a Tiling: New Results. 167-190 - Beniamino Di Martino:
Algorithmic Concept Recognition Support for Automatic Parallelization: A Case Study on Loop Optimization and Parallelization. 191-203 - Jenn-Yuan Tsai, Zhenzhen Jiang, Zhiyuan Li, David J. Lilja, Xin Wang, Pen-Chung Yew, Bixia Zheng, Stephen J. Schwinn:
Integrating Parallelizing Compilation Technology and Processor Architecture for Cost-Effective Concurrent multithreading. 205-222 - Sangho Ha, Heunghwan Kim:
KU-Loop Scheme: An Efficient Loop Unfolding Scheme for Multithreaded Computation. 223-236 - Chao-Tung Yang, Shian-Shyong Tseng, Ming-Huei Hsieh, Shih-Hung Kao:
Efficient Run-Time Parallelization for DO Loops. 237-253 - Tsung-Chuan Huang, Po-Hsueh Hsu, Tze-Nan Sheng:
Efficient Run-Time Scheduling for Parallelizing Partially Parallel Loops. 255-264 - Fermín Sánchez, Jordi Cortadella:
Reducing Register Pressure in Software Pipelining. 265-279 - Sheng-De Wang, Wei-Der Jwo:
Replication and Partitioning for Data Arrays in Distributed Memory Systems. 281-298
Volume 14, Number 2, June 1998
- Ching-Hung Wang, Tzung-Pei Hong, Shian-Shyong Tseng:
A New Hybrid Learning Algorithm for Non-Linear Boundaries. 305-325 - Tzung-Pei Hong, Shian-Shyong Tseng:
Primal-Dual Version Spaces for Acquisition of Disjunctive Concepts. 327-345 - Jonathan Lee, Lein F. Lai:
A New Apprach to Verifying Conceptual Models. 347-367 - Tzung-Pei Hong, Hong-Shung Wang:
Automatically Adjusting Crossover Ratios of Multiple Crossover Operators. 369-390 - Shyi-Ming Chen, Yuh-shih Shiau:
Vague Reasoning and Knowledge Repressentation Using Extended Fuzzy Petri Nets. 391-408
- Daniel Y. Chao:
Application of a Synthesis Algorithm to Flexible Manufacturing System. 409-447
- Yue-Li Wang, Kuo-Ching Chiang, Ming-Shing Yu:
Optimal Algorithms for Interval Graphs. 449-459
- Jung-Hong Chuang, Feng-Liang Lieh:
One and Two-Parameter Blending for Parametric Surfaces. 461-477
- Din-Chang Tseng, Hung-Pin Chiu, Jen-Chieh Cheng:
Ring Data for Invariant Recognition of Handwwritten Chinese Characters. 479-497
- Yunn Yen Chen, Jih-Kwon Peir, Chung-Ta King:
Performance of Shared Caches on Multithreaded Architectures. 499-514
Volume 14, Number 3, September 1998
- Martin Radetzki, Wolfram Putzke-Röming, Wolfgang Nebel:
A Unified Approach to Object-Oriented VHDL. 523-545 - Yee-Wing Hsieh, Steven P. Levitan:
Control / Data-Flow Analysis for VHDL Semantic Extraction. 547-565 - Shing-Wu Tung, Jing-Yang Jou:
A Logical Fault Model for Library Coherence Checking. 567-586 - Hiroto Yasuura, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar:
Embedded System Design Using Soft-Core Processor and Valen-C. 587-603 - Yin-Tsung Hwang, Yuan-Hung Wang, Jer-Sho Hwang:
Rapid Prototyping of Hardware / Software Codesign for Embedded Signal Processing. 605-632 - C.-J. Richard Shi:
Entity Overloading for Mixed-Signal Abstraction in VHDL. 633-644
- Kuen-Jong Lee, Wei-Lun Wang, Jhing-Fa Wang:
A General Structure of Feedback Shift Registers for Built-In Self Test. 645-667
- Wen Ching Wu, Chung-Len Lee, Jwu E. Chen:
A Two-Phase Fault Simulation Scheme for Sequential Circuits. 669-686
Volume 14, Number 4, December 1998
- Wen-Hsing Wei, Kuei-Ping Shih, Jang-Ping Sheu:
Compiling Array References with Affine Functions for Data-Parallel Programs. 695-723 - Ce-Kuen Shieh, Jyh-Chang Ueng, An-Chow Lai:
Design and Implementation of Cohesion. 725-741 - Jenn-Yang Ke, Jong-Chuang Tsay:
Finding Space-Optimal Linear Array for Uniform Dependence Algorithms with Arbitrary Convex Index Sets. 743-763 - Kuo-Hsuan Chen, Ge-Ming Chiu:
Fault-Tolerant Routing Algorithm for Meshes without Using Virtual Channels. 765-783 - Chao-Chin Wu, Cheng Chen:
A New Relaxed Memory Consistency Model for Shared-Memory Multiprocessors with Parallel-Multithreaded Processing Elements. 785-808 - Yu-Chee Tseng:
Multi-Node Broadcasting in Hypercubes and Star Graphs. 809-820
- Ing-Jer Huang:
A Case Study: Synthesis and Exploration of Instruction Set Design for Application-Specific Symbolic Computing. 821-842
- Jingtao Yao, Nicholas Teng, Hean-Lee Poh, Chew Lim Tan:
Forecasting and Analysis of Marketing Data Using Neural Networks. 843-862
- Kuen-Jong Lee, Cheng-Hsuing Kuo:
Concurrent Error Detection, Diagnosis, and Fault Tolerance for Switched-Capacitor Filters. 863-890
- Deng-Jyi Chen, Ming-Sang Chang, Ming-Cheng Sheng, Maw-Sheng Horng:
Time-Constrained Distributed Program Reliability Analysis. 891-911
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-18 20:35 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: