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Michaela Blott
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- affiliation: AMD Adaptive and Embedded Computing Group (AECG) Labs, Dublin, Ireland
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2020 – today
- 2024
- [j19]Allison McCarn Deiana, Nhan Tran, Joshua Agar, Michaela Blott, Giuseppe Di Guglielmo, Javier M. Duarte, Philip C. Harris, Scott Hauck, Mia Liu, Mark S. Neubauer, Jennifer Ngadiuba, Seda Ogrenci-Memik, Maurizio Pierini, Thea Aarrestad, Steffen Bähr, Jürgen Becker, Anne-Sophie Berthold, Richard J. Bonventre, Tomás E. Müller-Bravo, Markus Diefenthaler, Zhen Dong, Nick Fritzsche, Amir Gholami, Ekaterina Govorkova, Dongning Guo, Kyle J. Hazelwood, Christian Herwig, Babar Khan, Sehoon Kim, Thomas Klijnsma, Yaling Liu, Kin Ho Lo, Tri Nguyen, Gianantonio Pezzullo, Seyedramin Rasoulinezhad, Ryan A. Rivera, Kate Scholberg, Justin Selig, Sougata Sen, Dmitri Strukov, William Tang, Savannah Thais, Kai Lukas Unger, Ricardo Vilalta, Belinavon Krosigk, Shen Wang, Thomas K. Warburton:
Corrigendum: Applications and techniques for fast machine learning in science. Frontiers Big Data 6 (2024) - [j18]Lois Orosa
, Skanda Koppula
EcoFlow: Efficient Convolutional Dataflows on Low-Power Neural Network Accelerators. IEEE Trans. Computers 73(9): 2275-2289 (2024) - [j17]Zhiqiang Que
LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy Physics. ACM Trans. Embed. Comput. Syst. 23(2): 17:1-17:28 (2024) - [j16]Konstantin Hoßfeld
High-efficiency Compressor Trees for Latest AMD FPGAs. ACM Trans. Reconfigurable Technol. Syst. 17(2): 30:1-30:32 (2024) - [c41]Marius Meyer, Tobias Kenter, Lucian Petrica, Kenneth O'Brien, Michaela Blott, Christian Plessl:
Optimizing Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL. Euro-Par (2) 2024: 121-136 - [c40]Zhenhao He, Dario Korolija, Yu Zhu, Benjamin Ramhorst, Tristan Laan, Lucian Petrica, Michaela Blott, Gustavo Alonso:
ACCL+: an FPGA-Based Collective Engine for Distributed Applications. OSDI 2024: 211-231 - [i29]Marius Meyer, Tobias Kenter, Lucian Petrica, Kenneth O'Brien, Michaela Blott, Christian Plessl:
Optimizing Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL. CoRR abs/2403.18374 (2024) - 2023
- [j15]Timoteo García Bertoa
Fault-Tolerant Neural Network Accelerators With Selective TMR. IEEE Des. Test 40(2): 67-74 (2023) - [j14]Monica Chiosa, Thomas B. Preußer, Michaela Blott, Gustavo Alonso:
AMNES: Accelerating the computation of data correlation using FPGAs. Proc. VLDB Endow. 16(13): 4174-4187 (2023) - [j13]Syed Asad Alam
On the RTL Implementation of FINN Matrix Vector Unit. ACM Trans. Embed. Comput. Syst. 22(6): 94:1-94:27 (2023) - [e5]Irena Koprinska
Machine Learning and Principles and Practice of Knowledge Discovery in Databases - International Workshops of ECML PKDD 2022, Grenoble, France, September 19-23, 2022, Proceedings, Part I. Communications in Computer and Information Science 1752, Springer 2023, ISBN 978-3-031-23617-4 [contents] - [e4]Irena Koprinska
Machine Learning and Principles and Practice of Knowledge Discovery in Databases - International Workshops of ECML PKDD 2022, Grenoble, France, September 19-23, 2022, Proceedings, Part II. Communications in Computer and Information Science 1753, Springer 2023, ISBN 978-3-031-23632-7 [contents] - [i28]Shivam Aggarwal, Alessandro Pappalardo, Hans Jakob Damsgaard, Giuseppe Franco, Thomas B. Preußer, Michaela Blott, Tulika Mitra:
Post-Training Quantization with Low-precision Minifloats and Integers on FPGAs. CoRR abs/2311.12359 (2023) - [i27]Zhenhao He, Dario Korolija, Yu Zhu, Benjamin Ramhorst, Tristan Laan, Lucian Petrica, Michaela Blott, Gustavo Alonso:
ACCL+: an FPGA-Based Collective Engine for Distributed Applications. CoRR abs/2312.11742 (2023) - 2022
- [j12]Michaela Blott
Evaluating Theoretical Baselines for ML Benchmarking Across Different Accelerators. IEEE Des. Test 39(3): 28-36 (2022) - [j11]Allison McCarn Deiana, Nhan Tran
Applications and Techniques for Fast Machine Learning in Science. Frontiers Big Data 5: 787421 (2022) - [j10]Felix Jentzsch
RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures. IEEE Micro 42(6): 125-133 (2022) - [j9]Tobias Alonso
Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning. ACM Trans. Reconfigurable Technol. Syst. 15(2): 15:1-15:34 (2022) - [c39]Dana Diaconu, Lucian Petrica, Michaela Blott, Miriam Leeser:
Machine Learning Aided Hardware Resource Estimation for FPGA DNN Implementations. IPDPS Workshops 2022: 77-83 - [i26]Syed Asad Alam, David Gregg, Giulio Gambardella, Michael Preußer, Michaela Blott:
On the RTL Implementation of FINN Matrix Vector Compute Unit. CoRR abs/2201.11409 (2022) - [i25]Lois Orosa, Skanda Koppula, Yaman Umuroglu, Konstantinos Kanellopoulos, Juan Gómez-Luna, Michaela Blott, Kees A. Vissers, Onur Mutlu:
EcoFlow: Efficient Convolutional Dataflows for Low-Power Neural Network Accelerators. CoRR abs/2202.02310 (2022) - [i24]Alessandro Pappalardo, Yaman Umuroglu, Michaela Blott, Jovan Mitrevski, Benjamin Hawks, Nhan Tran, Vladimir Loncar, Sioni Summers, Hendrik Borras, Jules Muhizi, Matthew Trahms, Shih-Chieh Hsu, Scott Hauck, Javier M. Duarte:
QONNX: Representing Arbitrary-Precision Quantized Neural Networks. CoRR abs/2206.07527 (2022) - [i23]Hendrik Borras, Giuseppe Di Guglielmo, Javier M. Duarte, Nicolò Ghielmetti, Benjamin Hawks, Scott Hauck, Shih-Chieh Hsu, Ryan Kastner, Jason Liang, Andres Meza, Jules Muhizi, Tai Nguyen, Rushil Roy, Nhan Tran, Yaman Umuroglu, Olivia Weng, Aidan Yokuda, Michaela Blott:
Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark. CoRR abs/2206.11791 (2022) - [i22]Pedro J. Freire, Michael Anderson, Bernhard Spinnler, Thomas Bex, Jaroslaw E. Prilepsky, Tobias A. Eriksson, Nelson Costa, Wolfgang Schairer, Michaela Blott, Antonio Napoli
Towards FPGA Implementation of Neural Network-Based Nonlinearity Mitigation Equalizers in Coherent Optical Transmission Systems. CoRR abs/2206.12180 (2022) - [i21]Zhiqiang Que, Marcus Loo, Hongxiang Fan, Michaela Blott, Maurizio Pierini, Alexander D. Tapper, Wayne Luk:
LL-GNN: Low Latency Graph Neural Networks on FPGAs for Particle Detectors. CoRR abs/2209.14065 (2022) - [i20]Pedro J. Freire, Sasipim Srivallapanondh, Michael Anderson, Bernhard Spinnler, Thomas Bex, Tobias A. Eriksson, Antonio Napoli
Implementing Neural Network-Based Equalizers in a Coherent Optical Transmission System Using Field-Programmable Gate Arrays. CoRR abs/2212.04703 (2022) - 2021
- [j8]Alexandru-Lucian Georgescu
Performance vs. hardware requirements in state-of-the-art automatic speech recognition. EURASIP J. Audio Speech Music. Process. 2021(1): 28 (2021) - [j7]Murad Qasaimeh
Benchmarking vision kernels and neural network inference accelerators on embedded platforms. J. Syst. Archit. 113: 101896 (2021) - [j6]Michaela Blott
Evaluation of Optimized CNNs on Heterogeneous Accelerators Using a Novel Benchmarking Approach. IEEE Trans. Computers 70(10): 1654-1669 (2021) - [c38]Alberto Zeni
Optimized Implementation of the HPCG Benchmark on Reconfigurable Hardware. Euro-Par 2021: 616-630 - [c37]Zhenhao He, Daniele Parravicini, Lucian Petrica, Kenneth O'Brien, Gustavo Alonso, Michaela Blott:
ACCL: FPGA-Accelerated Collectives over 100 Gbps TCP-IP. H2RC@SC 2021: 33-43 - [e3]Michael Kamp
Machine Learning and Principles and Practice of Knowledge Discovery in Databases - International Workshops of ECML PKDD 2021, Virtual Event, September 13-17, 2021, Proceedings, Part I. Communications in Computer and Information Science 1524, Springer 2021, ISBN 978-3-030-93735-5 [contents] - [e2]Michael Kamp
Machine Learning and Principles and Practice of Knowledge Discovery in Databases - International Workshops of ECML PKDD 2021, Virtual Event, September 13-17, 2021, Proceedings, Part II. Communications in Computer and Information Science 1525, Springer 2021, ISBN 978-3-030-93732-4 [contents] - [i19]Allison McCarn Deiana, Nhan Tran, Joshua Agar, Michaela Blott, Giuseppe Di Guglielmo, Javier M. Duarte
Applications and Techniques for Fast Machine Learning in Science. CoRR abs/2110.13041 (2021) - 2020
- [c36]Yaman Umuroglu, Yash Akhauri, Nicholas J. Fraser, Michaela Blott:
High-Throughput DNN Inference with LogicNets. FCCM 2020: 238 - [c35]Tianyu Zhang
LPAC: A Low-Precision Accelerator for CNN on FPGAs. FPGA 2020: 316 - [c34]Michaela Blott, Johannes Kath, Lisa Halder, Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Miriam Leeser, Linda Doyle:
Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach. FPGA 2020: 317 - [c33]Yaman Umuroglu, Yash Akhauri, Nicholas James Fraser, Michaela Blott:
LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications. FPL 2020: 291-297 - [c32]Gurshaant Singh Malik, Lucian Petrica, Nachiket Kapre, Michaela Blott:
DarwiNN: efficient distributed neuroevolution under communication constraints. GECCO Companion 2020: 141-142 - [c31]Mairin Kroes, Lucian Petrica, Sorin Cotofana
Evolutionary bin packing for memory-efficient dataflow inference acceleration on FPGA. GECCO 2020: 1125-1133 - [c30]Lucian Petrica, Tobias Alonso, Mairin Kroes, Nicholas J. Fraser, Sorin Cotofana, Michaela Blott:
Memory-Efficient Dataflow Inference for Deep CNNs on FPGA. FPT 2020: 48-55 - [c29]Ussama Zahid, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Kees A. Vissers:
FAT: Training Neural Networks for Reliable Inference Under Hardware Faults. ITC 2020: 1-10 - [e1]João Gama
IoT Streams for Data-Driven Predictive Maintenance and IoT, Edge, and Mobile for Embedded Machine Learning - Second International Workshop, IoT Streams 2020, and First International Workshop, ITEM 2020, Co-located with ECML/PKDD 2020, Ghent, Belgium, September 14-18, 2020, Revised Selected Papers. Communications in Computer and Information Science 1325, Springer 2020, ISBN 978-3-030-66769-6 [contents] - [i18]Mairin Kroes, Lucian Petrica, Sorin Cotofana, Michaela Blott:
Evolutionary Bin Packing for Memory-Efficient Dataflow Inference Acceleration on FPGA. CoRR abs/2003.12449 (2020) - [i17]Yaman Umuroglu, Yash Akhauri, Nicholas J. Fraser, Michaela Blott:
LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications. CoRR abs/2004.03021 (2020) - [i16]Ussama Zahid, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Kees A. Vissers:
FAT: Training Neural Networks for Reliable Inference Under Hardware Faults. CoRR abs/2011.05873 (2020) - [i15]Lucian Petrica, Tobias Alonso, Mairin Kroes, Nicholas J. Fraser, Sorin Cotofana, Michaela Blott:
Memory-Efficient Dataflow Inference for Deep CNNs on FPGA. CoRR abs/2011.07317 (2020)
2010 – 2019
- 2019
- [j5]Michaela Blott
QuTiBench: Benchmarking Neural Networks on Heterogeneous Hardware. ACM J. Emerg. Technol. Comput. Syst. 15(4): 37:1-37:38 (2019) - [c28]Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, Martin Kumm, Peter Zipf
Efficient Error-Tolerant Quantized Neural Network Accelerators. DFT 2019: 1-6 - [c27]Yifan Yang, Qijing Huang
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. FPGA 2019: 23-32 - [i14]Michaela Blott, Lisa Halder, Miriam Leeser, Linda Doyle:
QuTiBench: Benchmarking Neural Networks on Heterogeneous Hardware. CoRR abs/1909.05009 (2019) - [i13]Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, Martin Kumm, Peter Zipf, Kees A. Vissers:
Efficient Error-Tolerant Quantized Neural Network Accelerators. CoRR abs/1912.07394 (2019) - 2018
- [j4]Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser
FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 11(3): 16:1-16:23 (2018) - [c26]Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas
Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic. ARC 2018: 29-42 - [c25]Julian Faraone, Nicholas J. Fraser, Michaela Blott, Philip H. W. Leong
SYQ: Learning Symmetric Quantization for Efficient Deep Neural Networks. CVPR 2018: 4300-4309 - [c24]Thomas B. Preußer, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott:
Inference of quantized neural networks on heterogeneous all-programmable devices. DATE 2018: 833-838 - [c23]Vladimir Rybalkin, Alessandro Pappalardo, Muhammad Mohsin Ghaffar, Giulio Gambardella, Norbert Wehn
FINN-L: Library Extensions and Design Trade-Off Analysis for Variable Precision LSTM Networks on FPGAs. FPL 2018: 89-96 - [c22]Julian Faraone, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Philip H. W. Leong
Customizing Low-Precision Deep Neural Networks for FPGAs. FPL 2018: 97-100 - [c21]Johannes de Fine Licht, Michaela Blott, Torsten Hoefler:
Designing scalable FPGA architectures using high-level synthesis. PPoPP 2018: 403-404 - [i12]Thomas B. Preußer, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott:
Inference of Quantized Neural Networks on Heterogeneous All-Programmable Devices. CoRR abs/1806.08085 (2018) - [i11]Julian Faraone, Nicholas J. Fraser, Michaela Blott, Philip Heng Wai Leong:
SYQ: Learning Symmetric Quantization For Efficient Deep Neural Networks. CoRR abs/1807.00301 (2018) - [i10]Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser:
Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic. CoRR abs/1807.03123 (2018) - [i9]Vladimir Rybalkin, Alessandro Pappalardo, Muhammad Mohsin Ghaffar, Giulio Gambardella, Norbert Wehn, Michaela Blott:
FINN-L: Library Extensions and Design Trade-off Analysis for Variable Precision LSTM Networks on FPGAs. CoRR abs/1807.04093 (2018) - [i8]Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung:
Accuracy to Throughput Trade-offs for Reduced Precision Neural Networks on Reconfigurable Logic. CoRR abs/1807.10577 (2018) - [i7]Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu:
FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks. CoRR abs/1809.04570 (2018) - [i6]Yifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer:
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. CoRR abs/1811.08634 (2018) - 2017
- [c20]Kenneth O'Brien, Lorenzo Di Tucci, Gianluca Durelli, Michaela Blott:
Towards exascale computing with heterogeneous architectures. DATE 2017: 398-403 - [c19]Lorenzo Di Tucci, Kenneth O'Brien, Michaela Blott, Marco D. Santambrogio:
Architectural optimizations for high performance and energy efficient Smith-Waterman implementation on FPGAs using OpenCL. DATE 2017: 716-721 - [c18]Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers:
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. FPGA 2017: 65-74 - [c17]Nicholas J. Fraser, Yaman Umuroglu, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong
Scaling Binarized Neural Networks on Reconfigurable Logic. PARMA-DITAM@HiPEAC 2017: 25-30 - [c16]Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser
Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic. ICCD 2017: 419-422 - [c15]Julian Faraone, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong
Compressing Low Precision Deep Neural Networks Using Sparsity-Induced Regularization in Ternary Networks. ICONIP (2) 2017: 393-404 - [i5]Nicholas J. Fraser, Yaman Umuroglu, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers:
Scaling Binarized Neural Networks on Reconfigurable Logic. CoRR abs/1701.03400 (2017) - [i4]Julian Faraone, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong:
Compressing Low Precision Deep Neural Networks Using Sparsity-Induced Regularization in Ternary Networks. CoRR abs/1709.06262 (2017) - [i3]Gustavo Alonso, Michaela Blott, Jens Teubner:
Databases on Future Hardware (Dagstuhl Seminar 17101). Dagstuhl Reports 7(3): 1-18 (2017) - 2016
- [c14]Michaela Blott:
Reconfigurable future for HPC. HPCS 2016: 130-131 - [c13]Giulia Guidi, Enrico Reggiani, Lorenzo Di Tucci, Gianluca Durelli, Michaela Blott, Marco D. Santambrogio:
On How to Improve FPGA-Based Systems Design Productivity via SDAccel. IPDPS Workshops 2016: 247-252 - [i2]Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers:
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. CoRR abs/1612.07119 (2016) - 2015
- [j3]Zsolt István, Gustavo Alonso, Michaela Blott, Kees A. Vissers:
A Hash Table for Line-Rate Data Processing. ACM Trans. Reconfigurable Technol. Syst. 8(2): 13:1-13:15 (2015) - [c12]David Sidler, Gustavo Alonso, Michaela Blott, Kimon Karras, Kees A. Vissers, Raymond Carley:
Scalable 10Gbps TCP/IP Stack Architecture for Reconfigurable Hardware. FCCM 2015: 36-43 - [c11]Michaela Blott, Ling Liu, Kimon Karras, Kees A. Vissers:
Scaling Out to a Single-Node 80Gbps Memcached Server with 40Terabytes of Memory. HotStorage 2015 - 2014
- [j2]Gianni Antichi
OSNT: open source network tester. IEEE Netw. 28(5): 6-12 (2014) - [i1]Kimon Karras, Michaela Blott, Kees A. Vissers:
High-Level Synthesis Case Study: Implementation of a Memcached Server. CoRR abs/1408.5387 (2014) - 2013
- [c10]Muhammad Shahbaz, Gianni Antichi
Architecture for an open source network tester. ANCS 2013: 123-124 - [c9]Zsolt István, Gustavo Alonso, Michaela Blott, Kees A. Vissers:
A flexible hash table design for 10GBPS key-value stores on FPGAS. FPL 2013: 1-8 - [c8]Michaela Blott, Kees A. Vissers:
Dataflow architectures for 10Gbps line-rate key-value-stores. Hot Chips Symposium 2013: 1-25 - [c7]Michaela Blott, Kimon Karras, Ling Liu, Kees A. Vissers, Jeremia Bär, Zsolt István:
Achieving 10Gbps Line-rate Key-value Stores with FPGAs. HotCloud 2013 - 2012
- [c6]John W. Lockwood, Adwait Gupte, Nishit Mehta, Michaela Blott, Tom English, Kees A. Vissers:
A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT). Hot Interconnects 2012: 9-16 - 2010
- [c5]John McGlone, Roger F. Woods
Design of a flexible high-speed FPGA-based flow monitor for next generation networks. ICSAMOS 2010: 37-44
2000 – 2009
- 2009
- [c4]Paul Edward McKechnie, Michaela Blott, Wim Vanderbauwhede:
Architectural Comparison of Instruments for Transaction Level Monitoring of FPGA-Based Packet Processing Systems. FCCM 2009: 175-182 - [c3]Paul Edward McKechnie, Michaela Blott, Wim Vanderbauwhede:
Automated instrumentation of FPGA-based systems for system-level transaction monitoring. SoC 2009: 168-171 - [c2]Paul Edward McKechnie, Michaela Blott, Wim Vanderbauwhede:
Debugging FPGA-based packet processing systems through transaction-level communication-centric monitoring. LCTES 2009: 129-136 - 2001
- [j1]Ronald L. Sharp, Michaela Blott, Michael J. Coss, Bruce K. Ellis, David L. Majette, Vinay Purohit:
Starburst: Building next-generation internet devices. Bell Labs Tech. J. 6(2): 6-17 (2001)
1990 – 1999
- 1998
- [c1]Michaela Blott, Hans Eberle:
A Networked Frame Buffer with Windows Management Support. EUROMEDIA 1998: 157-164
Coauthor Index
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