default search action
International Journal of Reconfigurable Computing, Volume 2011
Volume 2011, 2011
- Richard Veitch, Louis-Marie Aubert, Roger F. Woods
, Scott Fischaber:
FPGA Implementation of a Pipelined Gaussian Calculation for HMM-Based Large Vocabulary Speech Recognition. 697080:1-697080:10 - Emerson Carlos Pedrino, José Hiroki Saito, Valentin Obac Roda:
A Genetic Programming Approach to Reconfigure a Morphological Image Processing Architecture. 712494:1-712494:10 - Marcel Moscarelli Corrêa, Mateus Thurow Schoenknecht, Robson Dornelles, Luciano Volcan Agostini
A High-Throughput Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Targeting High-Definition Videos. 254730:1-254730:9 - Abel Guilhermino Silva-Filho, Filipe R. Cordeiro
An ESL Approach for Energy Consumption Analysis of Cache Memories in SoC Platforms. 219497:1-219497:12 - Phaklen EhKan, Tim Allen, Steven F. Quigley:
FPGA Implementation for GMM-Based Speaker Identification. 420369:1-420369:8 - Guilherme Perin, Daniel Gomes Mesquita, João Baptista dos Santos Martins:
Montgomery Modular Multiplication on Reconfigurable Hardware: Systolic versus Multiplexed Implementation. 127147:1-127147:10 - John Curreri, Greg Stitt
High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis. 406857:1-406857:17 - Elias Todorovich, Gustavo Sutter
Selected Papers from the Southern Programmable Logic Conference (SPL2010). 714761:1 - Alessio Montone, Marco D. Santambrogio
Floorplacement for Partial Reconfigurable FPGA-Based Systems. 483681:1-483681:12 - Christian Schuck, Bastian Haetzer, Jürgen Becker
Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs. 671546:1-671546:12 - Monica Magalhães Pereira, Luigi Carro
Dynamic Reconfigurable Computing: The Alternative to Homogeneous Multicores under Massive Defect Rates. 452589:1-452589:17 - Jorge L. Ortiz
A Streaming High-Throughput Linear Sorter System with Contention Buffering. 963539:1-963539:12 - Nachiket Kapre
An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads. 745147:1-745147:14 - Jeffrey Kingyens, J. Gregory Steffan:
The Potential for a GPU-Like Overlay Architecture for FPGAs. 514581:1-514581:15 - David Ndzi
An FPGA-Based Adaptable 200 MHz Bandwidth Channel Sounder for Wireless Communication Channel Characterisation. 894530:1-894530:14 - Markus Ferringer:
On Self-Timed Circuits in Real-Time Systems. 972375:1-972375:16 - Nikolaos Alachiotis
A Vector-Like Reconfigurable Floating-Point Unit for the Logarithm. 341510:1-341510:12 - G. Alonzo Vera, Marios S. Pattichis
A Dynamic Dual Fixed-Point Arithmetic Architecture for FPGAs. 518602:1-518602:19 - Loïc Lagadec
Experiment Centric Teaching for Reconfigurable Processors. 952560:1-952560:14 - Diana Göhringer, Jonathan Obie, André L. S. Braga, Michael Hübner, Carlos H. Llanos
Exploration of the Power-Performance Tradeoff through Parameterization of FPGA-Based Multiprocessor Systems. 985931:1-985931:17 - Alexander Klimm, Benjamin Glas, Matthias Wachs, Sebastian Vogel, Klaus D. Müller-Glaser, Jürgen Becker
A Security Scheme for Dependable Key Insertion in Mobile Embedded Devices. 820454:1-820454:19 - Matthias Birk, Clemens Hagner, Matthias Norbert Balzer, Nicole V. Ruiter
Evaluation of the Reconfiguration of the Data Acquisition System for 3D USCT. 952937:1-952937:9 - Ismail Ktata
Dynamic Application Model for Scheduling with Uncertainty on Reconfigurable Architectures. 156946:1-156946:15 - Diana Göhringer, Michael Hübner, Etienne Nguepi Zeutebouo, Jürgen Becker
Operating System for Runtime Reconfigurable Multiprocessor Systems. 121353:1-121353:16 - Benjamin Glas, Oliver Sander, Vitali Stuckert, Klaus D. Müller-Glaser, Jürgen Becker
Prime Field ECDSA Signature Processing for Reconfigurable Embedded Systems. 836460:1-836460:12 - Mateus B. Rutzig
Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment. 546962:1-546962:13 - Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi:
Exploration of Heterogeneous FPGA Architectures. 121404:1-121404:18 - Tobias Schumacher, Tim Süß, Christian Plessl
FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. 760954:1-760954:11 - Ikbel Belaid, Fabrice Muller, Maher Benjemaa:
Static Scheduling of Periodic Hardware Tasks with Precedence and Deadline Constraints on Reconfigurable Hardware Devices. 591983:1-591983:28 - Onur Derin, Erkan Diken, Leandro Fiorin:
A Middleware Approach to Achieving Fault Tolerance of Kahn Process Networks on Networks on Chips. 295385:1-295385:15 - Stefan Döbrich, Christian Hochberger:
Exploring Online Synthesis for CGRAs with Specialized Operator Sets. 601986:1-601986:22 - Mohsin Amin, Abbas Ramazani, Fabrice Monteiro, Camille Diou
A Self-Checking Hardware Journal for a Fault-Tolerant Processor Architecture. 962062:1-962062:15 - Aravind Dasu, João M. P. Cardoso
Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010). 574972:1-574972:2 - John Colby Hoffman, Marios S. Pattichis
A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback. 439072:1-439072:10 - Rawad N. Al-Haddad
Sustainable Modular Adaptive Redundancy Technique Emphasizing Partial Reconfiguration for Reduced Power Consumption. 430808:1-430808:25 - Dominique Blouin
AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC. 425401:1-425401:15 - Michael Hübner, Jürgen Becker, Loïc Lagadec
Selected Papers from the International Workshop on Reconfigurable Communication-Centric Systems on Chips (ReCoSoC' 2010). 865402:1 - Brian H. Pratt, Megan Fuller, Michael J. Wirthlin:
Reduced-Precision Redundancy on FPGAs. 897189:1-897189:12 - Omar Ahmed, Shawki Areibi, Karanvir Chattha, Ben Kelly:
PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability. 648483:1-648483:21 - Indranil Hatai
A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation. 342532:1-342532:10
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-02 21:16 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: